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    Journal: Formal Methods in System Design

    Volume 7, Issue 1/2

    7 -- 25David M. Russinoff. A Formalization of a Subset of VHDL in the Boyer-Moore Logic
    27 -- 51Peter T. Breuer, Luis Sánchez Fernández, Carlos Delgado Kloos. A Simple Denotational Semantics, Proof Theory and a Validation Condition Generator for Unit-Delay VHDL
    53 -- 71Dominique Borrione, Ashraf M. Salem. Denotational Semantics of a Synchronous VHDL Subset
    73 -- 99Ralf Reetz, Thomas Kropf. A Flowgraph Semantics of VHDL: Toward a VHDL Verification Workbench in HOL
    101 -- 123Serafín Olcoz, José Manuel Colom. A Colored Petri Net Model of VHDL
    125 -- 148Gert Döhmen, Ronald Herrmann, Hergen Pargmann. Translating VHDL into Functional Symbolic Finite-State Models
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