Journal: Formal Methods in System Design

Volume 7, Issue 3

155 -- 226Scott F. Smith, Amy E. Zwarico. Correct Compilation of Specifications to Deterministic Asynchronous Circuits
227 -- 241Patrice Godefroid, Gerard J. Holzmann, Didier Pirottin. State-Space Caching Revisited
243 -- 259Huimin Lin. PAM: A Process Algebra Manipulator

Volume 7, Issue 1/2

7 -- 25David M. Russinoff. A Formalization of a Subset of VHDL in the Boyer-Moore Logic
27 -- 51Peter T. Breuer, Luis Sánchez Fernández, Carlos Delgado Kloos. A Simple Denotational Semantics, Proof Theory and a Validation Condition Generator for Unit-Delay VHDL
53 -- 71Dominique Borrione, Ashraf M. Salem. Denotational Semantics of a Synchronous VHDL Subset
73 -- 99Ralf Reetz, Thomas Kropf. A Flowgraph Semantics of VHDL: Toward a VHDL Verification Workbench in HOL
101 -- 123Serafín Olcoz, José Manuel Colom. A Colored Petri Net Model of VHDL
125 -- 148Gert Döhmen, Ronald Herrmann, Hergen Pargmann. Translating VHDL into Functional Symbolic Finite-State Models