Journal: IEICE Electronic Express

Volume 17, Issue 10

20200090 -- 0Chenji Liu, Lan Chen, Xiaoran Hao, Mao Ni, Hao Sun. Fast cacheline-based data replacement for hybrid DRAM and STT-MRAM main memory
20200093 -- 0Yoshiaki Narusue, Yoshihiro Kawahara, Hiroyuki Morikawa. Load optimization factors for analyzing the efficiency of wireless power transfer systems using two-port network parameters
20200094 -- 0Zhongjie Guo, Ningmei Yu, Longsheng Wu. An improved segmented DAC for column readout circuit correction of large array CMOS image sensor
20200097 -- 0Zhenwei Zhang, Lei Qiu, Yi Shan, Yemin Dong. A 16-bit 8-MS/s SAR ADC with a foreground calibration and hybrid-charge-supply power structure
20200101 -- 0Chenyu Wang, Kengo Iokibe, Yoshitaka Toyota. Mitigating differential skew by rotating meshed ground for high-density layout in flexible printed circuits
20200102 -- 0Sai Li, Jianwei Han, Rui Chen, Shipeng Shangguan, Yingqi Ma, Xuan Wang. Study on the single-event upset sensitivity of 65-nm CMOS sequential logic circuit
20200109 -- 0Zhenwei Zhang, Yi Shan, Yemin Dong. A 16 bit 200 kS/s successive approximation register ADC with foreground on-chip self-calibration
20200112 -- 0Takefumi Yoshikawa, Tatsuya Iwata, Junji Shibazaki, Sho Muroga, Hiroaki Ikeda. A charge recycling stacked I/O in standard CMOS technology for wide TSV data bus
20200121 -- 0Sizhen Li, Kai Yu, Li-xiang Ou, Pan Zhou, Gary Zhang. A compact hybrid envelope tracking supply modulator with wide-band high-slew-rate linear amplifier