Journal: IJES

Volume 3, Issue 4

199 -- 208Thorsten Dräger, Gerhard Fettweis. Application-specific permutation networks
209 -- 218Terry Tao Ye, Giovanni De Micheli. On-chip implementation of multiprocessor networks and switch fabrics
219 -- 228Zhijie Jerry Shi, Xiao Yang, Ruby B. Lee. Alternative application-specific processor architectures for fast arbitrary bit permutations
229 -- 240Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle. Hardware implementation of an elliptic curve processor over GF(p) with Montgomery modular multiplier
241 -- 255Hans Eberle, Nils Gura, Sheueling Chang Shantz, Vipul Gupta. A cryptographic processor for arbitrary elliptic curves over GF(2:::m:::)
256 -- 262Piia Saastamoinen, Ilkka Saastamoinen, Jari Nurmi. Code compression in DSP processor systems
263 -- 270P. H. Chan, Jack Y. B. Lee. An efficient disk-array-based server design for a multicast video streaming system
271 -- 284Anne-Claire Guillou, Patrice Quinton, Tanguy Risset. Hardware synthesis for systems of recurrence equations with multidimensional schedule
285 -- 293José Luis Ayala, Marisa López-Vallejo, Carlos A. López-Barrio, Alexander V. Veidenbaum. A hardware mechanism to reduce the energy consumption of the register file of in-order architectures
294 -- 303Herbert Bos, Bart Samwel, Mihai-Lucian Cristea, Kostas Anagnostakis. Safe execution of untrusted applications on embedded network processors

Volume 3, Issue 3

109 -- 118Andreas Wieferink, Tim Kogel, Olaf Zerres, Rainer Leupers, Heinrich Meyr. SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends
119 -- 127Jong-eun Lee, Kiyoung Choi, Nikil Dutt. Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures
128 -- 140Vikram Chandrasekhar, Frank Livingston, Joseph R. Cavallaro. Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers
141 -- 149Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero. Power-efficient VLIW design using clustering and widening
150 -- 159Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Heinrich Meyr. Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips
160 -- 169Pablo Robelly, Gordon Cichon, H. Ahlendorf, Gerhard Fettweis. A HW/SW design methodology for embedded SIMD vector signal processors
170 -- 180Steven Derrien, Alexandru Turjan, Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere. Deriving efficient control in Process Networks with Compaan/Laura
181 -- 196Andy D. Pimentel. The Artemis workbench for system-level performance evaluation of embedded systems

Volume 3, Issue 1/2

3 -- 7Christian W. Probst, Ulrich Kremer, Luca Benini, Peter Schelkens. Power-aware computing systems
8 -- 16Jerry Hom, Ulrich Kremer. Inter-program optimisations for disk energy reduction
17 -- 30Vasanth Venkatachalam, Michael Franz, Christian W. Probst. A new way of estimating compute-boundedness and its application to dynamic voltage scaling
31 -- 42Chunling Hu, Daniel A. Jiménez, Ulrich Kremer. An evaluation infrastructure for power and energy optimisations
43 -- 51Giacomo Paci, Francesco Poletti, Luca Benini, Paul Marchal. Exploring temperature-aware design in low-power MPSoCs
52 -- 64Aman Gayasen, Suresh Srinivasan, Narayanan Vijaykrishnan, Mahmut T. Kandemir. Design of power-aware FPGA fabrics
65 -- 72Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem. Power management in external memory using PA-CDRAM
73 -- 82José L. Ayala, Marisa López-Vallejo, David Atienza, Praveen Raghavan, Francky Catthoor, Diederik Verkest. Energy-aware compilation and hardware design for VLIW embedded systems
83 -- 92Gaurav Singh, Sandeep K. Shukla. Algorithms for low power hardware synthesis from Concurrent Action Oriented Specifications (CAOS)
93 -- 106Matthias Grumer, Christian Steger, Manuel Wendt, Andreas Mühlberger, Ulrich Neffe. Horizontal and vertical HW/SW co-design flows for power aware smart card designs