Journal: Integration

Volume 39, Issue 2

63 -- 0Kaushik Roy. Guest Editorial
64 -- 89Bipul Chandra Paul, Amit Agarwal, Kaushik Roy. Low-power design techniques for scaled technologies
90 -- 112Jia Di, Jiann S. Yuan, Ronald F. DeMara. Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design
113 -- 130David Atienza, Stylianos Mamagkakis, Francesco Poletti, Jose Manuel Mendias, Francky Catthoor, Luca Benini, Dimitrios Soudris. Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems
131 -- 155Matthias Müller, Sven Simon, Holger Gryska, Andreas Wortmann, Steffen Buch. Low power synthesizable register files for processor and IP cores