External Links

    Journal: Integration

    Volume 9, Issue 3

    223 -- 0Lambert Spaanenburg. Editorial
    225 -- 242Sanjay V. Rajopadhye, Richard M. Fujimoto. Automating the design of systolic arrays
    243 -- 257Xianjin Yao, C. L. Liu. PLA logic minimization by simulated annealing
    259 -- 269Youn-Long Lin, Yu-Chin Hsu. A new algorithm for tile generation
    271 -- 285Yeong-Yil Yang, Chong-Min Kyung. An efficient algorithm for optimal PLA folding
    287 -- 302Graham M. Megson, David J. Evans. The systolic control ring instruction processor (SCRIP)
    303 -- 319Wei Wang, Craig K. Rushforth. VLSI implementation of a 16-state coset code
    321 -- 338Robert Tjärnström. Switch-level simulation based on local decisions

    Volume 9, Issue 2

    107 -- 0Lambert Spaanenburg. Editorial
    109 -- 127Sreejit Chakravarty. Testing of non-feedback bridging faults
    129 -- 139Alan A. Bertossi. A VLSI system for string matching
    141 -- 161Izidor Gertner, Moshe Shamash. VLSI architectures to compute the Wigner Distribution
    163 -- 177Dian Zhou. An optimum channel routing algorithm in the restricted wire overlap model
    179 -- 197Arnold Ginetti, Charles Trullemans. k - D) control unit architectures
    199 -- 214Jingsheng Cong, D. F. Wong. Generating more compactable channel routing solutions

    Volume 9, Issue 1

    1 -- 0Lambert Spaanenburg. Editorial
    3 -- 23C. C. Su, Majid Sarrafzadeh. Optimal gate-matrix layout of CMOS functional cells
    25 -- 47P. Gee, Min-You Wu, S. M. Kang, Ibrahim N. Hajj. A metal - metal matrix cell generator for multi-level metal MOS technology
    49 -- 80Bruce F. Cockburn, Janusz A. Brzozowski. Switch-level testability of the dynamic CMOS PLA
    81 -- 97Tony M. Carter, Kent F. Smith, Steven R. Jacobs, Richard M. Neff. Cell matrix methodologies for integrated circuit design
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