Journal: J. Inf. Sci. Eng.

Volume 14, Issue 4

695 -- 723Wen-Hsing Wei, Kuei-Ping Shih, Jang-Ping Sheu. Compiling Array References with Affine Functions for Data-Parallel Programs
725 -- 741Ce-Kuen Shieh, Jyh-Chang Ueng, An-Chow Lai. Design and Implementation of Cohesion
743 -- 763Jenn-Yang Ke, Jong-Chuang Tsay. Finding Space-Optimal Linear Array for Uniform Dependence Algorithms with Arbitrary Convex Index Sets
765 -- 783Kuo-Hsuan Chen, Ge-Ming Chiu. Fault-Tolerant Routing Algorithm for Meshes without Using Virtual Channels
785 -- 808Chao-Chin Wu, Cheng Chen. A New Relaxed Memory Consistency Model for Shared-Memory Multiprocessors with Parallel-Multithreaded Processing Elements
809 -- 820Yu-Chee Tseng. Multi-Node Broadcasting in Hypercubes and Star Graphs
821 -- 842Ing-Jer Huang. A Case Study: Synthesis and Exploration of Instruction Set Design for Application-Specific Symbolic Computing
843 -- 862Jingtao Yao, Nicholas Teng, Hean Lee Poh, Chew Lim Tan. Forecasting and Analysis of Marketing Data Using Neural Networks
863 -- 890Kuen-Jong Lee, Cheng-Hsuing Kuo. Concurrent Error Detection, Diagnosis, and Fault Tolerance for Switched-Capacitor Filters
891 -- 911Deng-Jyi Chen, Ming-Sang Chang, Ming-Cheng Sheng, Maw-Sheng Horng. Time-Constrained Distributed Program Reliability Analysis

Volume 14, Issue 3

523 -- 545Martin Radetzki, Wolfram Putzke-Röming, Wolfgang Nebel. A Unified Approach to Object-Oriented VHDL
547 -- 565Yee-Wing Hsieh, Steven P. Levitan. Control / Data-Flow Analysis for VHDL Semantic Extraction
567 -- 586Shing-Wu Tung, Jing-Yang Jou. A Logical Fault Model for Library Coherence Checking
587 -- 603Hiroto Yasuura, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar. Embedded System Design Using Soft-Core Processor and Valen-C
605 -- 632Yin-Tsung Hwang, Yuan-Hung Wang, Jer-Sho Hwang. Rapid Prototyping of Hardware / Software Codesign for Embedded Signal Processing
633 -- 644C.-J. Richard Shi. Entity Overloading for Mixed-Signal Abstraction in VHDL
645 -- 667Kuen-Jong Lee, Wei-Lun Wang, Jhing-Fa Wang. A General Structure of Feedback Shift Registers for Built-In Self Test
669 -- 686Wen Ching Wu, Chung-Len Lee, Jwu E. Chen. A Two-Phase Fault Simulation Scheme for Sequential Circuits

Volume 14, Issue 2

305 -- 325Ching-Hung Wang, Tzung-Pei Hong, Shian-Shyong Tseng. A New Hybrid Learning Algorithm for Non-Linear Boundaries
327 -- 345Tzung-Pei Hong, Shian-Shyong Tseng. Primal-Dual Version Spaces for Acquisition of Disjunctive Concepts
347 -- 367Jonathan Lee, Lein F. Lai. A New Apprach to Verifying Conceptual Models
369 -- 390Tzung-Pei Hong, Hong-Shung Wang. Automatically Adjusting Crossover Ratios of Multiple Crossover Operators
391 -- 408Shyi-Ming Chen, Yuh-shih Shiau. Vague Reasoning and Knowledge Repressentation Using Extended Fuzzy Petri Nets
409 -- 447Daniel Y. Chao. Application of a Synthesis Algorithm to Flexible Manufacturing System
449 -- 459Yue-Li Wang, Kuo-Ching Chiang, Ming-Shing Yu. Optimal Algorithms for Interval Graphs
461 -- 477Jung-Hong Chuang, Feng-Liang Lieh. One and Two-Parameter Blending for Parametric Surfaces
479 -- 497Din-Chang Tseng, Hung-Pin Chiu, Jen-Chieh Cheng. Ring Data for Invariant Recognition of Handwwritten Chinese Characters
499 -- 514Yunn Yen Chen, Jih-Kwon Peir, Chung-Ta King. Performance of Shared Caches on Multithreaded Architectures

Volume 14, Issue 1

7 -- 26Jing-Chiou Liou, Michael A. Palis. On the Effectiveness of Compiler-Time Scheduling Approaches for Distributed Memory Multiprocessor
27 -- 51S. K. S. Gupta, S. Drishnamurthy. An Interprocedural Framework for Determining Efficient Array Data Redistributeions
53 -- 78Chien-Min Wang, Yomin Hou, Chiu-Yu Ku. Compiler Techniques for Minimizing Link Contention of Linear-Constant Communication on k-ary n-cubes
79 -- 105Pangfeng Liu, Jan-Jan Wu. Supporting Efficieent Tree Structures for Distributed Scientific Computation
107 -- 138Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Meenakshi A. Kandaswamy. Locality Optimization Algorithms for Compilation of Out-of-Core Codes
139 -- 165Yin-Tsung Hwang, Jer-Sho Hwang. Simulated Evolution Based Parallel Code Generation for Programmable DSP Processors
167 -- 190Frederic Desprez, Jack Dongarra, Fabrice Rastello, Yves Robert. Determining the Idle Time of a Tiling: New Results
191 -- 203Beniamino Di Martino. Algorithmic Concept Recognition Support for Automatic Parallelization: A Case Study on Loop Optimization and Parallelization
205 -- 222Jenn-Yuan Tsai, Zhenzhen Jiang, Zhiyuan Li, David J. Lilja, Xin Wang, Pen-Chung Yew, Bixia Zheng, Stephen J. Schwinn. Integrating Parallelizing Compilation Technology and Processor Architecture for Cost-Effective Concurrent multithreading
223 -- 236Sangho Ha, Heunghwan Kim. KU-Loop Scheme: An Efficient Loop Unfolding Scheme for Multithreaded Computation
237 -- 253Chao-Tung Yang, Shian-Shyong Tseng, Ming-Huei Hsieh, Shih-Hung Kao. Efficient Run-Time Parallelization for DO Loops
255 -- 264Tsung-Chuan Huang, Po-Hsueh Hsu, Tze-Nan Sheng. Efficient Run-Time Scheduling for Parallelizing Partially Parallel Loops
265 -- 279Fermín Sánchez, Jordi Cortadella. Reducing Register Pressure in Software Pipelining
281 -- 298Sheng-De Wang, Wei-Der Jwo. Replication and Partitioning for Data Arrays in Distributed Memory Systems