| 0 | -- | 0 | Mario Stevens. Chairman's introduction |
| 1 | -- | 2 | D. Q. M. Fay. Opening address: Hardware and software in system engineering |
| 3 | -- | 0 | G. A. Schwippert. Keynote address K1: Small and medium sized industries (SMI) |
| 5 | -- | 0 | J. A. Dinklo. Keynote address K2: The strategic importance of microcomputing for the business environment |
| 9 | -- | 16 | M. Malek. Keynote address K3: Responsive systems (the challenge for the nineties) |
| 17 | -- | 0 | Robert V. Adams. Keynote address K4: The state of global printing in the '90s |
| 21 | -- | 32 | Arthus I. Karshmer, James N. Thomas, P. K. Annaiyappa, D. Eshner, S. Kankanahalli, G. Kurup. Architectural support for operating systems: A popular RISC vs. a popular CISC |
| 33 | -- | 39 | Franck Cappello, Jean-Luc Béchennec, Daniel Etiemble. A risc central processing unit for a massivelly parallel architecture |
| 41 | -- | 48 | Djamshid Tavangarian, M. Beck. ASTRA: An associative RISC-Architecture |
| 51 | -- | 57 | Dimitris E. Metafas, Costas E. Goutis. A DSP processor with a powerful set of elementary arithmetic operations based on cordic and CCM algorithms |
| 59 | -- | 65 | Thomas Kropf, J. Fröbetal, W. Beller, T. Giesler. A hardware implementation of a modified DES-algorithm |
| 67 | -- | 74 | Walter Bragagnini, Paolo Guazzoni, Maurizio Pitalieri, Luisa Zetta. Computational logic unit for a microprogrammed data acquisition system: an evaluation prototype |
| 75 | -- | 0 | J. Tiberghien. Parallel Applications |
| 77 | -- | 84 | Wouter Joosen, Yolande Berbers, Pierre Verbaeten. Dynamic load balancing in transputer applications with geometric parallelism |
| 85 | -- | 92 | Valmir C. Barbosa, Maria Cristina S. Boeres. An Occam-based evaluation of a parallel version of simulated annealing |
| 93 | -- | 100 | Hong Shen. Occam implementation of path-disjoint routing on the Hathi-2 transputer system |
| 103 | -- | 108 | Christian Ewering, Gunter Gerhardt. PASS: High level synthesis |
| 109 | -- | 116 | Björn Lisper. The interactive space-time scheduler |
| 117 | -- | 124 | A. J. W. M. ten Berg. Stepwise decomposition in controlpath synthesis |
| 127 | -- | 133 | William A. Geideman, Roger A. Niederland, David L. Harrington. A 32-bit RISC CPU implemented in GaAs |
| 135 | -- | 142 | J. E. H. M. Bormans, Willem J. Withagen, F. P. M. Budzelaar, M. P. J. Stevens. Designing high performance instruction caches in VLSI |
| 143 | -- | 150 | Olatz Arregi, Clemente Rodríguez, Amaia Ibarra. Evaluation of the optimal strategy for managing the register file |
| 151 | -- | 0 | D. Wilson. Session B: Signal - II |
| 153 | -- | 158 | M. Maresca, G. Carravieri, G. Cornara, Arrigo L. Frisiani. Partitioned algorithms for gaussian elimination on reconfigurable processor arrays |
| 159 | -- | 165 | H. Bekker, M. Renardus. Design of a transputer network for searching neighbours in M.D. simulations |
| 167 | -- | 174 | Eric Lindemann, Miller S. Puckette, Eric Viara, Michel Starkier. The IRCAM signal processing workstation - An environment for research in real-time musical signal processing and performance |
| 177 | -- | 183 | R. J. Huis in 't Veld. The role of languages in the design-trajectory |
| 185 | -- | 192 | Gerd Kock. Towards the verification of optimizing transformations for imperative programs |
| 193 | -- | 198 | Andrea Domenici. Petri nets in logic |
| 201 | -- | 206 | J. Vlahavas, Andreas S. Pombortsis, D. Stamatis. Towards a parallel inference machine: the APIM project |
| 207 | -- | 214 | Cosimo Antonio Prete. A new solution of coherence protocol for tightly coupled multiprocessor systems |
| 215 | -- | 220 | Erik F. Dirkx, Frank Verboven, Jacques Tiberghien. Distributed simulation of computer networks |
| 223 | -- | 229 | Jean-Luc Dubois, Przemyslaw Bakowski, Adam Pawlak. Synthesis of programmable control structures for a simulation speed-up |
| 231 | -- | 236 | S. Balakrishnan, S. K. Nandy. Quasi dynamic approach to layout compaction |
| 237 | -- | 240 | N. A. Kyrloglou, Odysseas G. Koufopavlou, Costas E. Goutis. A generator for a number format conversion IC |
| 241 | -- | 246 | Ad. C. Verschueren. An object oriented design and simulation system for VLSI |
| 249 | -- | 255 | Bernard Faure, Guy Mazaré. A cellular architecture dedicated to neural net emulation |
| 257 | -- | 262 | J. Hoekstra. System architecture of a modular neural network using 400 simple processors |
| 263 | -- | 270 | Lambert Spaanenburg, A. J. Beltman, J. A. G. Nijhuis, A. Reitsma. A case study in the migration of software to hardware using basics |
| 273 | -- | 280 | Antti Auer, Mikko Levanto, Ari Okkonen, Jyrki Okkonen. Solution in software crisis |
| 281 | -- | 288 | Ian R. McChesney, Derrick Glass, John G. Hughes. Case tool support for requirements capture and analysis |
| 289 | -- | 296 | Timo Jokela, Kai Lindberg. Statecharts based requirements analysis: Deriving user oriented models |
| 297 | -- | 302 | Jari Arkko, Vesa Hirvisalo, Juha Kuusela, Esko Nuutila. Supporting testing of specifications and implementations |
| 305 | -- | 312 | Lech Józwiak. Simultaneous decompositions of sequential machines |
| 313 | -- | 319 | Mikael R. K. Patel. Random logic circuit implementation of extended Timed Petri Nets |
| 321 | -- | 329 | M. P. J. Stevens, F. P. M. Budzelaar. System level VLSI design |
| 333 | -- | 339 | K. Parthenis, C. Metaxaki-Kossionidis, B. Dimitriadis. EIKON: A software library for image processing applications |
| 341 | -- | 346 | C. E. Prakash, S. K. Nandy. VOXEL based modeling and rendering irregular solids |
| 347 | -- | 353 | P. Pitot, B. Moisan, Yves Duthen, René Caubet. A transputer based implementation of the VOXAR project |
| 357 | -- | 364 | Gerardo Canfora, Aniello Cimitile, Ugo de Carlini. Reverse engineering and data flow diagrams in ADA environment |
| 365 | -- | 370 | Nelson Q. Vasconcelos, Edil S. T. Fernandes, Fernando M. B. Barbosa. An environment for parallel programming in PASCAL |
| 371 | -- | 378 | Andrea Clematis, Gabriella Dodero, Vittoria Gianuzzi. Recovery meta program in Unix based environment |
| 381 | -- | 388 | T. S. Hughes, Jim E. Cooling. Animation prototyping of formal specifications of real-time systems |
| 389 | -- | 396 | J. S. Sagoo, D. J. Holding. The specification and design of hard real-time systems using timed and temporal petri nets |
| 397 | -- | 402 | Charles Andre, Luc Fancelli. A mixed implementation of a real-time system |
| 405 | -- | 412 | Giacomo Buonanno, A. Burri, Franco Fummi, Donatella Sciuto. An approach to a design for testability personal consultant |
| 413 | -- | 419 | Paolo Camurati, Antonio Lioy, Paolo Prinetto, Matteo Sonza Reorda. Assessing the diagnostic power of test pattern sets |
| 421 | -- | 428 | Paolo Camurati, Tiziana Margaria, Paolo Prinetto. The OTTER environment for resolution-based proof of hardware correctness |
| 431 | -- | 438 | P. B. Franken, Ad J. Van de Goor. Special architecture for high-performance scan conversion |
| 439 | -- | 445 | Luís Vieira de de Sá, Vítor Silva 0001, Fernando Perdigão, Sérgio Faria, Pedro Assunção. A parallel architecture for real-time video coding |
| 447 | -- | 454 | Ferenc Vajda. Application and implementation of window-based image processing algorithms |
| 457 | -- | 465 | A. T. Balou, Apostolos Nikolaos Refenes. Designing a parallel object-oriented compiler target language (TOOL) |
| 467 | -- | 474 | Michel Auguin, Fernand Boéri, C. Carrière, G. Menez. From program to hardware: A parallel architecture compiler |
| 475 | -- | 481 | E. Accomazzo, M. Ancona, R. Bobbio, C. Cagnassi, L. Paolin. Integrating intermediate code optimization with retargetable code generation |
| 483 | -- | 0 | Wolfgang A. Halang. Session E4: Real Time Systems II |
| 485 | -- | 490 | Monika Kapus-Kolar. Constructing real-time multi-channel protocols |
| 491 | -- | 497 | Stephen C. Winter, Derek R. Wilson, D. F. Neale. Real-time functional programming systems |
| 499 | -- | 506 | David Scholefield, Hussein Zedan. TAM: Temporal agent model for real-time distributed systems |
| 509 | -- | 512 | Olaf Stern, Heinrich Theodor Vierhaus. CMOS layout generation for improved testability |
| 513 | -- | 520 | Henrique Madeira, Gonçalo Quadros, João Gabriel Silva. Experimental evaluation of a set of simple error detection mechanisms |
| 521 | -- | 527 | Tassos Markas, Nick Kanopoulos. A bus-monitor unit for fault-tolerant system configurations |
| 529 | -- | 534 | Gianpiero Cabodi, Silvano Gai, Matteo Sonza Reorda. A transputer-based gate-level fault simulator |
| 537 | -- | 544 | Peter J. de Graaff. On the formal specification and verification of digital circuits |
| 545 | -- | 553 | Stefano Antoniazzi, Mirella Mastretti. An interactive environment for hardware/software system design at the specification level |
| 555 | -- | 560 | Edwige E. Pissaloux. A rational methodology for design of new computer structures |
| 561 | -- | 566 | Uwe Wienkop. Behavioral circuit description on system level |
| 569 | -- | 576 | Edwige E. Pissaloux, Samir Bouaziz, Alain Mérigot, Francis Devos. Co-programming: A tool for the development of software for massively parallel computers |
| 577 | -- | 584 | Peter Buhler. The COIN model for concurrent computation and its implementation |
| 585 | -- | 591 | Andrew M. Tyrrell, Geoffrey F. Carpenter. Data flow methods in the design of parallel computing systems |
| 593 | -- | 597 | T. J. G. Benson, Peter Milligan, N. S. Scott. Program development within the mathematician's devil |
| 601 | -- | 608 | Ranjani Narayan, V. Rajaraman. Performance analysis of a multiprocessor machine based on data flow principles |
| 609 | -- | 616 | Emilio L. Zapata, José Carlos Cabaleiro, Ramon Doallo, Francisco Argüello. Systolic architecture for the calculation of the correlation coefficients |
| 617 | -- | 623 | Jie Xu, Shize Huang. A new comparison-based scheme for multiprocessor fault tolerance |
| 627 | -- | 635 | Arthur I. Karshmer, James N. Thomas, James M. Phelan. TVNet II: A cable TV based metropolitan area network using the KEDS protocol |
| 637 | -- | 644 | Jong K. Ahn, Song C. Moon. Join optimization in distributed databases on broadcast network |
| 645 | -- | 653 | Apostolos Nikolaos Refenes. Message passing via singly-buffered channels: an efficient & flexible communications control mechanism |
| 657 | -- | 664 | Jean-Luc Dekeyser, Philippe Marquet, Philippe Preux. Vector addressing processor for direct and indirect accesses |
| 665 | -- | 672 | J. P. C. F. H. Smeets, W. J. Withagen, M. P. J. Stevens. Pipelining a memory based CISC processor |
| 675 | -- | 682 | Geoffrey M. Macharia, James Austin. A performance analysis of toroidal mesh networks |
| 683 | -- | 691 | Ryszard F. Gajda, Miroslaw Thor, Marek Tudruj. Enhancing a control graph based HDL for performance evaluation of simulated architectures |
| 695 | -- | 701 | Geoffrey F. Carpenter. The synthesis of deadlock-free interprocess communications |
| 703 | -- | 712 | P. Pramanik, Pradip K. Das, A. K. Bandyopadhyay, D. Q. M. Fay. A deadlock-free communication kernel for loop connected message passing computer architecture |