External Links

    Journal: Journal of Systems Architecture

    Volume 56, Issue 9

    407 -- 418Luis Morales-Velazquez, René de Jesús Romero-Troncoso, Roque Alfredo Osornio-Rios, Gilberto Herrera Ruiz, Eduardo Cabal-Yepez. Open-architecture system based on a reconfigurable hardware-software multi-agent platform for CNC machines
    419 -- 428Jong Wook Kwak, Young Tae Jeon. Compressed tag architecture for low-power embedded cache systems
    429 -- 441Antonio Flores, Manuel E. Acacio, Juan L. Aragón. Exploiting address compression and heterogeneous interconnects for efficient message management in tiled CMPs
    442 -- 451M. Vanegas, Matteo Tomasi, Javier Díaz, Eduardo Ros Vidal. Multi-port abstraction layer for FPGA intensive memory exploitation applications
    452 -- 462Minghua Tang, Xiaola Lin. Quarter Load Threshold (QLT) flow control for wormhole switching in mesh-based Network-on-Chip
    463 -- 473Jianguo Yao, Xue Liu, Zonghua Gu, Xiaorui Wang, Jian Li. Online adaptive utilization control for real-time embedded multiprocessor systems
    474 -- 486Yosi Ben-Asher, Nadav Rotem, Eddie Shochat. Finding the best compromise in compiling compound loops to Verilog

    Volume 56, Issue 8

    303 -- 304Juan Antonio Gómez Pulido. Recent advances in Hardware/Software co-design
    305 -- 316A. Ahmad, B. Krill, A. Amira, H. Rabah. Efficient architectures for 3D HWT using dynamic partial reconfiguration
    317 -- 326Usman Ali, Mohammad Bilal Malik. Hardware/software co-design of a real-time kernel based tracking system
    327 -- 339Alejandro Castillo Atoche, D. Torres Roman, Y. Shkvarko. Towards real time implementation of reconstructive signal processing algorithms using systolic arrays coprocessors
    340 -- 351Tao Li, Wu Jigang, Siew Kei Lam, Thambipillai Srikanthan, Xicheng Lu. Selecting profitable custom instructions for reconfigurable processors
    352 -- 367Da-Ren Chen, Chiun-Chieh Hsu, You-Shyang Chen, Chi-Jung Kuo, Lin-Chih Chen. Transition-aware DVS algorithm for real-time systems using tree structure analysis
    368 -- 383Jonghee M. Youn, Minwook Ahn, Yunheung Paek, Jongwung Kim, Jeonghun Cho. Two versions of architectures for dynamic implied addressing mode
    384 -- 391Chen Fu, Dongxin Wen, Xiaoqun Wang, Xiao-Zong Yang. Hardware transactional memory: A high performance parallel programming model
    392 -- 406Quentin L. Meunier, Frédéric Pétrot, Jean-Louis Roch. Hardware/software support for adaptive work-stealing in on-chip multiprocessor

    Volume 56, Issue 7

    221 -- 222Juan Antonio Gómez Pulido. From systems to networks on chip: A promising research area in the Hardware/Software co-design
    223 -- 232Sébastien Le Beux, Guy Bois, Gabriela Nicolescu, Youcef Bouchebaba, Michel Langevin, Pierre G. Paulin. Combining mapping and partitioning exploration for NoC-based embedded systems
    233 -- 241Ser-Hoon Lee, Yeo-Chan Yoon, Sun Young Hwang. Communication-aware task assignment algorithm for MPSoC using shared memory
    242 -- 255Amit Kumar Singh, Thambipillai Srikanthan, Akash Kumar, Wu Jigang. Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms
    256 -- 264Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, Zainalabedin Navabi. EDXY - A low cost congestion-aware routing algorithm for network-on-chips
    265 -- 277Ahsan Shabbir, Akash Kumar, Sander Stuijk, Bart Mesman, Henk Corporaal. CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications
    278 -- 292Mouna Baklouti, Yassine Aydi, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid. Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
    293 -- 302Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo. Reconfigurable Networks on Chip: DRNoC architecture

    Volume 56, Issue 4-6

    151 -- 162Abu Asaduzzaman, Fadi N. Sibai, Manira Rani. Improving cache locking performance of modern embedded systems via the addition of a miss table at the L2 cache level
    163 -- 179Luís Nogueira, Luís Miguel Pinho. A capacity sharing and stealing strategy for open real-time systems
    180 -- 190Hui Guo, Sri Parameswaran. Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems
    191 -- 207José M. Claver, P. Agustí, Miguel Arevalillo-Herráez, G. León, Manel Canseco. A reconfigurable platform for evaluating the performance of QoS networks
    208 -- 220Hyunchul Park, Dongkun Shin. Buffer flush and address mapping scheme for flash memory solid-state disk

    Volume 56, Issue 2-3

    77 -- 87Alberto Ros, Manuel E. Acacio, José M. García. A scalable organization for distributed directories
    88 -- 102Chun-Hsian Huang, Pao-Ann Hsiung, Jih-Sheng Shen. UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems
    103 -- 115Sebastian Lange, Martin Middendorf. Multi-level reconfigurable architectures in the switch model
    116 -- 123Jason Van Dyken, José G. Delgado-Frias. FPGA schemes for minimizing the power-throughput trade-off in executing the Advanced Encryption Standard algorithm
    124 -- 135Matthew Areno, Brandon Eames, Joshua Templin. A Force-Directed Scheduling based architecture generation algorithm and design tool for FPGAs
    136 -- 149Keoncheol Shin, Hwansoo Han, Kwang-Moo Choe. Composition-based Cache simulation for structure reorganization

    Volume 56, Issue 12

    641 -- 653Soojun Im, Dongkun Shin. ComboFTL: Improving performance and lifespan of MLC flash memory using SLC flash buffer
    654 -- 666Yosi Ben-Asher, Jawad Haj-Yihia. Computing the correct Increment of Induction Pointers with application to loop unrolling
    667 -- 684Anderson Kuei-An Ku, Jingling Xue, Yong Guan. Gather/scatter hardware support for accelerating Fast Fourier Transform
    685 -- 695Rodrígo González-Alberquilla, Fernando Castro, Luis Piñuel, Francisco Tirado. Stack filter: Reducing L1 data cache power consumption

    Volume 56, Issue 11

    543 -- 544Ignacio Bravo, Marco D. Santambrogio. Design flows and system architectures for adaptive computing on reconfigurable platforms
    545 -- 560Chun-Hsian Huang, Pao-Ann Hsiung, Jih-Sheng Shen. Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption
    561 -- 576Sven-Ole Voigt, Malte Baesler, Thomas Teufel. Dynamically reconfigurable dataflow architecture for high-performance digital signal processing
    577 -- 587Matteo Tomasi, F. Barranco, M. Vanegas, Javier Díaz, Eduardo Ros Vidal. Fine grain pipeline architecture for high performance phase-based optical flow computation
    588 -- 596Roberto Gutierrez, V. Torres, Javier Valls-Coquillat. FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques
    597 -- 615Balal Ahmad, Ali Ahmadinia, Tughrul Arslan. High level modeling and automated generation of heterogeneous SoC architectures with optimized custom reconfigurable cores and on-chip communication media
    616 -- 622Jose Brizuela, Alberto Ibañez, Carlos Fritsch. NDE system for railway wheel inspection in a standard FPGA
    623 -- 632Mahmood Fazlali, Mojtaba Sabeghi, Ali Zakerolhosseini, Koen Bertels. Efficient task scheduling for runtime reconfigurable systems
    633 -- 640Cesar Pedraza, Emilio Castillo, Javier Castillo, José Luis Bosque, José Ignacio Martínez, Oscar David Robles, Javier Cano, Pablo Huerta. Content-based image retrieval algorithm acceleration in a low-cost reconfigurable FPGA cluster

    Volume 56, Issue 10

    487 -- 499Bhanu Pisupati, Geoffrey Brown. Embedded software debugging using virtual filesystem abstractions
    500 -- 508Haibing Guan, Bo Liu, Zhengwei Qi, Yindong Yang, Hongbo Yang, Alei Liang. CoDBT: A multi-source dynamic binary translator using hardware-software collaborative techniques
    509 -- 522Kristoffer Nyborg Gregertsen, Amund Skavhaug. Implementing the new Ada 2005 timing event and execution time control features on the AVR32 architecture
    523 -- 533Hongzhen Xu, Guosun Zeng. Specification and verification of dynamic evolution of software architectures
    534 -- 542Jianbo Dong, Lei Zhang 0008, Yinhe Han, Guihai Yan, Xiaowei Li. Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling

    Volume 56, Issue 1

    1 -- 15Yuan-Shin Hwang, Jia-Jhe Li. On reducing load/store latencies of cache accesses
    16 -- 26Mahmoud Moadeli, Alireza Shahrabi, Wim Vanderbauwhede, Partha P. Maji. An analytical performance model for the Spidergon NoC with virtual channels
    27 -- 37Young-Ho Seo, Hyun-Jun Choi, Ji-Sang Yoo, Dong Wook Kim. An architecture of a high-speed digital hologram generator based on FPGA
    38 -- 47Claudio Brunelli, Fabio Garzia, Davide Rossi, Jari Nurmi. A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations
    48 -- 62George Kornaros. A soft multi-core architecture for edge detection and data analysis of microarray images
    63 -- 74Manel Velasco, Pau Martí, Josep M. Fuertes, Camilo Lozoya, Scott A. Brandt. Experimental evaluation of slack management in real-time control systems: Coordinated vs. self-triggered approach
    75 -- 0Gyungho Lee, Yixin Shi. Erratum to Access region cache with register guided memory reference partitioning [Journal of Systems Architecture 55 (2009) 434-445]
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