| 5 | -- | 0 | J. Luu. Comments on 'A comparison of RISC architectures' by R.S. Piepho and W.S. Wu |
| 8 | -- | 11 | Richard H. Stern. Micro Law-software patents |
| 14 | -- | 25 | Hideto Hidaka, Yoshio Matsuda, Mikio Asakura, Kazuyasu Fujishima. The cache DRAM architecture: a DRAM with an on-chip cache memory |
| 26 | -- | 38 | Katsuyuki Kaneko, Masaitsu Nakajima, Yasuhiro Kakakura, Junji Nishikawa, Ichiro Okabayashi, Hiroshi Kadota. Processing element design for a parallel computer |
| 40 | -- | 55 | Yuji Hatano, Shinichiro Yano, Hiroyuki Mori, Hiroji Yamada, Mikio Hirano, Ushio Kawabe. A 4-bit, 250-MIPS processor using Josephson technology |
| 56 | -- | 69 | Hiraoki Kaneko, Nariko Suzuki, Hiroshi Wabuka, Koji Maemura. Realizing the V80 and its system support functions |
| 70 | -- | 85 | Milan Milenkovic. Microprocessor memory management units |