| 407 | -- | 436 | Michitaka Kameyama, Takahiro Hanyu, Takafumi Aoki. Multiple-Valued Logic as a New Computing Paradigm - A Brief Survey of Higuchi's Researchon Multiple-Valued Logic |
| 437 | -- | 465 | Shinobu Nagayama, Alan Mishchenko, Tsutomu Sasao, Jon T. Butler. Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams |
| 467 | -- | 479 | Tetsuya Uemura, Masafumi Yamamoto. Four-Valued Magnetic Random Access Memory Based on Magneto Tunnel Junction and Resonant Tunneling Diode |
| 481 | -- | 497 | Akira Mochizuki, Takahiro Hanyu, Michitaka Kameyama. Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic |
| 499 | -- | 517 | Tomohiro Takahashi, Takahiro Hanyu. Control Signal Multiplexing Based Asynchronous Data Transfer Scheme Using Multiple-Valued Bidirectional Current-Mode Circuits |
| 519 | -- | 544 | Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi. Design of Multiple-Valued Logic Circuits Using Graph-Based Evolutionary Synthesis |
| 545 | -- | 565 | Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi. Prototype Fabrication of Field-Programmable Digital Filter LSIs Using Multiple-Valued Current-Mode Logic - Device Scaling and Future Prospects |
| 567 | -- | 602 | Mozammel H. A. Khan, Marek A. Perkowski, Mujibur R. Khan, Pawel Kerntopf. Terary GFSOP Minimization Using Kronecker Decision Diagrams and Their Synthesis with Quantum Cascades |
| 603 | -- | 618 | Yasushi Yuminaka. Intra/Inter-Chip CDMA Communications for Efficient Data Transmission Towards New Paradigm of Computing |
| 619 | -- | 632 | Takahiro Hanyu, Shunichi Kaeriyama, Michitaka Kameyama. Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic |