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0 | -- | 0 | Jerzy Proficz. All-gather Algorithms Resilient to Imbalanced Process Arrival Patterns |
0 | -- | 0 | Matthew Tomei, Shomit Das, Mohammad Seyedzadeh, Philip Bedoukian, Bradford M. Beckmann, Rakesh Kumar 0002, David A. Wood 0001. Byte-Select Compression |
0 | -- | 0 | Tobias Gysi, Christoph Müller, Oleksandr Zinenko, Stephan Herhut, Eddie Davis, Tobias Wicky, Oliver Fuhrer, Torsten Hoefler, Tobias Grosser. Domain-Specific Multi-Level IR Rewriting for GPU: The Open Earth Compiler for GPU-accelerated Climate Simulation |
0 | -- | 0 | Joscha Benz, Oliver Bringmann 0001. Scenario-Aware Program Specialization for Timing Predictability |
0 | -- | 0 | An Zou, Huifeng Zhu, Jingwen Leng, Xin He, Vijay Janapa Reddi, Christopher D. Gill, Xuan Zhang 0001. System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery System |
0 | -- | 0 | Wonik Seo, Sanghoon Cha, Yeonjae Kim, Jaehyuk Huh, Jongse Park. SLO-Aware Inference Scheduler for Heterogeneous Processors in Edge Platforms |
0 | -- | 0 | Kaustav Goswami 0002, Dip Sankar Banerjee, Shirshendu Das. Towards Enhanced System Efficiency while Mitigating Row Hammer |
0 | -- | 0 | Rui Xu, Sheng Ma, Yaohua Wang, Xinhai Chen, Yang Guo 0003. Configurable Multi-directional Systolic Array Architecture for Convolutional Neural Networks |
0 | -- | 0 | Yasir Mahmood Qureshi, William Andrew Simon, Marina Zapater, Katzalin Olcoz, David Atienza. Gem5-X: A Many-core Heterogeneous Simulation Platform for Architectural Exploration and Optimization |
0 | -- | 0 | Shounak Chakraborty 0001, Magnus Själander. WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption |
0 | -- | 0 | Zhibing Sha, Jun Li 0062, Lihao Song, Jiewen Tang, Min Huang, Zhigang Cai, Lianju Qian, Jianwei Liao, Zhiming Liu 0001. Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs |
0 | -- | 0 | Tina Jung, Fabian Ritter 0002, Sebastian Hack. PICO: A Presburger In-bounds Check Optimization for Compiler-based Memory Safety Instrumentations |
0 | -- | 0 | Aninda Manocha, Tyler Sorensen 0001, Esin Tureci, Opeoluwa Matthews, Juan L. Aragón, Margaret Martonosi. GraphAttack: Optimizing Data Supply for Graph Applications on In-Order Multicore Architectures |
0 | -- | 0 | Syed Asad Alam, James Garland, David Gregg. Low-precision Logarithmic Number Systems: Beyond Base-2 |
0 | -- | 0 | Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook. SortCache: Intelligent Cache Management for Accelerating Sparse Data Workloads |
0 | -- | 0 | Paul Metzger, Volker Seeker, Christian Fensch, Murray Cole. Device Hopping: Transparent Mid-Kernel Runtime Switching for Heterogeneous Systems |
0 | -- | 0 | Candace Walden, Devesh Singh, Meenatchi Jagasivamani, Shang Li 0001, Luyi Kang, Mehdi Asnaashari, Sylvain Dubois, Bruce L. Jacob, Donald Yeung. Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache |
0 | -- | 0 | M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Keshab K. Parhi, Jianping Wang 0006, Sachin S. Sapatnekar, Ulya R. Karpuzcu. Spiking Neural Networks in Spintronic Computational RAM |
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