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Journal: IEEE Transactions on Computers

Volume 17, Issue 11

1027 -- 1037Frank A. Russo, Robert J. Valek. Process Performance Computer for Adaptive Control Systems
1037 -- 1043Robert H. Mitchell, Thomas Williams, William D. Ryan. A Delay Line and Logic Circuits Utilizing Charge-Storage Subharmonic Parametric Oscillators
1044 -- 1061Giovanni B. Gerace. Digital System Design Automation - A Method for Designing a Digital System as a Sequential Network System
1062 -- 1065Sigurd Waaben. High-Speed, Interlaced WRITE and READ-Only Operation of a Plated-Wire Memory System
1066 -- 1073Akio Sasaki. The Basis for Implementation of Ad idive Operations in the Residue Number System
1074 -- 1080Giuseppe Fantauzzi. NORNAND Maitra Cascades
1081 -- 1088Yao Tung Yen. Some Theoretical Properties of Multithreshold Realizable Functions
1089 -- 0Albert W. Small. Partitions and Edge-Weighted Pair-Graphs
1090 -- 0M. G. Harman. An Attempt to Design an Improved Multiplication System
1091 -- 1092Edward S. Davidson, Gernot Metze. Comments on "An Algorithm for Synthesis of Multiple-Output Combinational Logic"
1093 -- 1095Edward G. Coffman Jr., Martin S. Schmookler. A Random-Walk Model of a Queue Storage Problem
1098 -- 0Jay Earley. R68-46 Use of Transition Matrices in Compiling
1098 -- 1099D. W. Fife. R68-47 Computer Scheduling Methods and Their Countermeasures
1099 -- 0William M. Newman. R68-48 A Multiprogramming Monitor for Small Machines
1099 -- 0W. C. McGee. R68-49 Virtual Memory Processes and Sharing in Multics
1100 -- 0Charles L. Jackson. R68-50 Multiprogramming System Performance Measurement and Analysis
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