Journal: IEEE Transactions on Computers

Volume 17, Issue 9

822 -- 826Yao Tung Yen. A Mathematical Model Characterizing Four-Phase MOS Circuits for Logic Simulation
827 -- 845Tsai Hwa Chen. The Use of Delay Lines in Reading a Manchester Code
845 -- 849Thammavarapu R. N. Rao. Error-Checking Logic for Arithmetic-Type Operations of a Processor
850 -- 861James R. Duley, Donald L. Dietmeyer. A Digital System Design Language (DDL)
861 -- 872Stephen Sik-Sang Yau, John M. Schumpert. Design of Pattern Classifiers with the Updating Property Using Stochastic Approximation Techniques
873 -- 880Marvin Perlman. The Synthesis of Binary Sequence Detectors
881 -- 884Eduardo Kellerman. A Formula for Logical Network Cost
885 -- 886Jochen Beister. On the Implementation of Failure-Tolerant Counters
887 -- 889Chin Chin Tung. A Division Algorithm for Signed-Digit Arithmetic
889 -- 893Rodger L. Gamblin. An Analysis of High-Speed, Linear-Passive Binary, Read-Only Stores
893 -- 894Rodger L. Gamblin, Cyril J. Tunis. A High-Speed Threshold Memory Element
894 -- 896Celso de Renna e Souza. A Note on Embedding Nonlinear Machines
897 -- 898Marshall C. Y. Kuo. Solution of Nonlinear Equations
899 -- 900P. K. Sinha Roy. 1
899 -- 0Joseph S. Rosko. Comments on "Hybrid Computer Solution of Optimal Control Problems by the Maximum Principle"
922 -- 923Chester C. Carroll. R68-40 Sequential Machines and Automata Theory
923 -- 924J. H. Saltzer. R68-41 Development of Executive Routines, Both Hardware and Software
924 -- 0Beverly F. Char, Ccodie S. Wells. R68-42 On Designing Generalized File Records for Management Information Systems
924 -- 0J. C. Strauss. R68-43 Two Continuous System Modelling Programs

Volume 17, Issue 8

721 -- 728Charles A. David, Bernhard Feldman. High-Speed Fixed Memories Using Large-Scale Integrated Resistor Matrices
729 -- 737Gustav N. Wassel. Multiple Reflections from RC Loading of Pulse-Signal Transmission Lines
738 -- 746John Harley. The Linear Transformer Tree
746 -- 757George H. Barnes, Richard M. Brown, Maso Kato, David J. Kuck, Daniel L. Slotnick, Richard A. Stokes. The ILLIAC IV Computer
758 -- 770David J. Kuck. ILLIAC IV Software and Application Programming
770 -- 782Nicolae N. Necula. An Algorithm for the Automatic Approximate Minimization of Boolean Functions
782 -- 788K. L. Suryanarayanan, A. C. Soudack. Analog Computer Automatic Parameter Optimization of Nonlinear Control Systems with Specific Inputs
788 -- 789Caxton C. Foster. Determination of Priority in Associative Memories
789 -- 792Gerald P. Cardillo, King-sun Fu. On Suboptimal Sequential Pattern Recognition
792 -- 795Igal Kohavi, Zvi Kohavi. Variable-Length Distinguishing Sequences and Their Application to the Design of Fault-Detection Experiments
795 -- 798A. Bouchet. An Algebraic Method for Minimizing the Number of States in an Incomplete Sequential Machine
802 -- 0Frank M. Brown. The Origin of the Method of Iterated Consensus
818 -- 0Robert M. McClure. R68-36 Dataless Programming
818 -- 819Ivan Flores. R68-37 Intercommunication of Processors and Memory
819 -- 820Arthur I. Rubin. R68-39 Simulation of the Transfer Function of a Crustacean Muscle Bundle
819 -- 0S. P. Bingulac. R68-38 Accurate Analog Computer Generation of Bessel Functions for Large Ranges

Volume 17, Issue 7

621 -- 634Harold E. Maurer, Robert C. Ricci. Horizons in Guidance Computer Component Technology
635 -- 639John K. Russell. A Visual Image Processor
640 -- 648Kuo A. Chen. Computer Aided Memory Design Using Transmission Line Models
649 -- 655Franco P. Preparata. Convolutional Transformation and Recovery of Binary Sequences
656 -- 667William S. Meisel. Variable-Threshold Threshold Elements
667 -- 676William S. Meisel. Nets of Variable-Threshold Threshold Elements
676 -- 683Frederick F. Sellers Jr., Mu-Yue Hsiao, LeRoy W. Bearnson. Analyzing Errors with the Boolean Difference
684 -- 691Sergio P. Colussi, Giovanni V. Pallottino. An Approach to Optimum Tolerance Adaptive Threshold Elements
691 -- 693Bently A. Crane. Path Finding with Associative Memory
693 -- 694Shmuel Winograd. A New Algorithm for Inner Product
694 -- 696Edward L. Renschler. A Variable Counter Design Technique
696 -- 697Eugene Levine. On the Characterizing Parameters of a Threshold Function
697 -- 699Monroe M. Newborn. A Synthesis Technique for Binary Input-Binary Output Synchronous Sequential Moore Machines
701 -- 702Sureshchander. Comments on "RST Flip-Flop Input Equations"
702 -- 0Kenneth A. Foster. Comments on "Basic Properties and a Construction Method for Fail-Safe Logical Systems"
702 -- 0Hisashi Mine, Yoshihaki Koga. 3
718 -- 719Omri Serlin. R68-33 PHENO: A New Concept of Hybrid Computing Elements
718 -- 0Omri Serlin. R68-32 The IADIC: A Hybrid Computing Element
719 -- 0Martin Y. Silberberg. R68-34 Hybrid Apollo Docking Simulation
719 -- 720E. J. Copes. R68-35 Optimal Generation of Arbitrary Functions

Volume 17, Issue 6

525 -- 536Walter W. Wierwille, James R. Knight. Off-Line Correlation Analysis of Nonstationary Signals
537 -- 542Richard O. McCary. An Approximation to the Asymmetric Strip-Line Coupling Coefficient
542 -- 550René M. G. Wijnhoven. A Simple High-Speed Magnetic Access Switch Matrix
551 -- 558David L. Greer. Characterization of the Magnetic Second-Harmonic Analog Memory
559 -- 566Arthur D. Friedman, Premachandran R. Menon. Synthesis of Asynchronous Sequential Circuits with Multiple-Input Changes
566 -- 578J. D. Bargainer Jr., Clarence L. Coates. Minimal Multiplexed Threshold Gate Realizations
578 -- 591Donald L. Dietmeyer. Bounds on the Period of Oscillatory Activity in Randomly Interconnected Networks of Neuron-Like Elements
592 -- 596Václav Dvorák. A Two-Rail Cascade Synthesis of Boolean Functions
596 -- 599Richard C. Born, Allan K. Scidmore. Transformation of Switching Functions to Completely Symmetric Switching Functions
600 -- 0Narsingh Deo. Generalized Parallel Redundancy in Digital Computers
600 -- 603Edward G. Coffman Jr., A. C. McKellar. On the Motion of an Unbounded, Markov Queue in Random Access Storage
606 -- 0Alfred V. Aho. R68-27 Programming Languages for Automata
607 -- 608Warren D. Little. R68-30 Monte Carlo Solution of Partial Differential Equations Using a Hybrid Computer
607 -- 0Don Darms. R68-29 Hydro System Optimization Model
607 -- 0W. M. McKeeman. R68-28 A Microprogrammed Implementation of EULER on IBM System/360 Model 30
608 -- 0Robert Gleman. R68-31 The Effect of Digital Compensation for Computation Delay in a Hybrid Loop

Volume 17, Issue 5

421 -- 431Wayne A. Davis. Single Shift-Register Realizations for Sequential Machines
432 -- 442Angelo Raffaele Meo. Modular Tree Structures
443 -- 451William H. Kautz, Karl N. Levitt, Abraham Waksman. Cellular Interconnection Arrays
452 -- 461Taylor L. Booth. Statistical Properties of Random Digital Sequences
461 -- 469Hwa C. Torng. An Algorithm for Finding Secondary Assignments of Synchronous Sequential Circuits
470 -- 475James C. Miller, Charles M. Wine. A Simple Display for Characters and Graphics
476 -- 485Harold W. Lawson Jr.. Programming-Language-Oriented Instruction Streams
485 -- 491Richard R. Shively. A Digital Processor to Generate Spectra in Real Time
492 -- 503Richard G. Casey, George Nagy. An Autonomous Reading Machine
503 -- 506Stephen R. Sedore. More Efficient Use of the F Matrix in Practical Circuit Analysis Programs
506 -- 508Martin S. Schmookler. High-Speed Binary-to-Decimal Conversion
520 -- 521J. L. Smith. R68-20 Effects of Scheduling on File Memory Applications
520 -- 0Gio Wiederhold. R68-19 Bulk Core in a 360/67 Time Sharing System
521 -- 0Masao Kato. R68-21 System Architecture for Large Scale Integration
521 -- 522T. A. Murrell. R68-22 Current Status of Large Scale Integration Technology
522 -- 523William M. Waite. R68-24 A Proposal for Definitions in ALGOL
522 -- 0David J. Kuck. R68-23 The Greenblatt Chess Program
523 -- 524Ben B. Barnes. R68-26 Some Techniques for Accuracy Improvement in Analog Computation
523 -- 0H. A. Freedman. R68-25 An On-Line Editor

Volume 17, Issue 4

301 -- 308R. A. Manske. Computor Simulation of Narrowband Systems
309 -- 312Donald R. Haring. On Shift-Register Realizations of Sequential Machines and Finite-State Universal Sequential Machines
312 -- 324C. C. Su, Stephen Sik-Sang Yau. Unitary Shift-Register Realizations of Sequential Machines
325 -- 329Clarence M. Ablow, Michael Yoeli, James Turner. Irreducible Decompositions of Transformation Graphs by Assignment Techniques
330 -- 337James L. Massey, Michael K. Sain. Inverses of Linear Sequential Circuits
338 -- 351Shuzo Yajima, Toshihide Ibaraki. Realization of Arbitrary Logic Functions by Completely Monotonic Functions and Its Applications to Threshold Logic
352 -- 366William H. Kautz. Fault Testing and Diagnosis in Combinational Digital Circuits
367 -- 372Fred W. Smith. Pattern Classifier Design by Linear Programming
373 -- 375Harry Andrews. A High-Speed Algorithm for the Computer Generation of Fourier Transforms
375 -- 379Stephen J. Kahne. Sensitivity-Function Calculation in Linear Systems Using Time-Shared Analog Integration
380 -- 382Amos Nathan, Jonathan Molcho. Improved Voltage Selector and Cascade Multiplier Circuits
382 -- 385S. B. Matthews. Generation of Pseudorandom Noise Having a Gaussian Spectral Density
385 -- 0John V. Wait. Correction to "State-Space Methods for Designing Digital Simulations of Continuous Fixed Linear Systems"
385 -- 391S. Yajima, Toshihide Ibaraki, I. Kawano. On Autonomous Logic Nets of Threshold Elements
391 -- 399Stephen Sik-Sang Yau, Daniel L. Ostapko. Realization of a Class of Switching Functions by Threshold-Logic Networks
399 -- 401John H. Munson, Richard O. Duda, Peter E. Hart. Experiments with Highleyman's Data
402 -- 0John L. Douce. Comment on "Computation of Time-Phase Displacements of Binary Linear Sequence Generators"
405 -- 0Dennis W. Fife. R68-10 SODAS and a Methodology for System Design
405 -- 406Hugh C. Lauer. R68-11 Intercommunication of Processors and Memory
406 -- 407Norman R. Nielsen. R68-12 An Experimental Model of System/ 360
407 -- 0Gary D. Hornbuckle. R68-13 An Introduction to Computer Graphic Terminals
407 -- 408Frank G. Curl. R68-14 Microprogrammed Control in Problem-Oriented Languages
408 -- 0Edward E. Markson. R68-15 Trajectory Computation by a Hybrid Computer for the Apollo Midcourse Abort Simulation
409 -- 410Clark F. Crocker. R68-17 Synthesis of Resistive Digital-to-Analog Conversion Ladders for Arbitrary Codes with Fixed Positive Weights
409 -- 0Donald T. Greenwood. R68-16 A Mathematical Model for the Investigation of Three-Dimensional Fields with Asymmetric Boundaries
410 -- 0Brian R. Gaines. R68-18 Random Pulse Machines

Volume 17, Issue 3

205 -- 214Charles H. Thomas. Transport Time-Delay Simulation for Transmission Line Representation
214 -- 229Shuzo Yajima, Toshihide Ibaraki. A Theory of Completely Monotonic Functions and its Applications to Threshold Logic
229 -- 237Azaria Paz, Bezalel Peleg. On Concatenative Decompositions of Regular Events
238 -- 251A. Bart Howe, Clarence L. Coates. Logic Hazards in Threshold Networks
251 -- 259H. Allen Curtis. Polylinear Sequential Circuit Realizations of Finite Automata
259 -- 267Barry M. Epstein. A 48-Channel PCM Tape Data-Acquisition System
268 -- 270William Thomas Marquitz, Y. Tokad. On Improving the Analog Computer Solutions of Linear Systems
270 -- 272K. Doty, H. Frank. A Theorem on Linearity
273 -- 0Stanley R. Petrick, George C. Sethares. On the Determination of Complete Sets of Logical Functions
273 -- 279Martin A. Fischler, Meyer Tannenbaum. Assumptions in the Threshold Synthesis of Symmetric Switching Functions
279 -- 283P. K. Sinha Roy. A Slide Rule Device for Checking 2-Summability
283 -- 284J. Kella, A. Shani. On the Reversibility of Computations in a Digital Differential Analyzer
298 -- 300Lee C. Thomas. R68-9 A Computer Simulation of Electrical Loss and Loading Effect in Magnetic Recording
298 -- 0Ralph E. Keirstead. R68-8 Language Directed Computer Design

Volume 17, Issue 2

113 -- 116E. James Angelo Jr., John Logan, Kenneth W. Sussman. The Separation Technique: A Method for Simulating Transistors to Aid Integrated Circuit Design
117 -- 128Peter R. Schneider, Donald L. Dietmeyer. An Algorithm for Synthesis of Multiple-Output Combinational Logic
129 -- 134Douglas B. Armstrong, Arthur D. Friedman, Premachandran R. Menon. Realization of Asynchronous Sequential Circuits Without Inserted Delay Elements
134 -- 135Sheldon B. Akers Jr.. On Maximum Inversion with Minimum Inverters
136 -- 145Domenico Ferrari. Fast Carry-Propagation Iterative Networks
146 -- 151Stephen H. Unger. A Row Assignment for Delay-Free Realizations of Flow Tables Without Essential Hazards
152 -- 173Rocco H. Urbano. Structure and Function in Polyfunctional Nets
174 -- 178Thomas J. McAvoy. Least-Square Dead-Time Approximations
178 -- 182William G. Wee, King-sun Fu. An Adaptive Procedure for Multiclass Pattern Classification
182 -- 184Charles M. Allen, Donald D. Givone. A Minimization Technique for Multiple-Valued Logic Systems
184 -- 186Peter Weiner, Thomas F. Dwyer. Discussion of Some Flaws in the Classical Theory of Two-Level Minimization of Multiple-Output Switching Networks
188 -- 0Victor Azgapetian. Comment on "An Analog Photoresistive Multiplier"
188 -- 0Mark E. Connelly. 2
191 -- 192Donald L. Epley. R68-5 Models of Computational Systems-Cyclic to Acyclic Graph Transformations
192 -- 0B. C. Biega. R68-7 Analog Simulation of Ferroresonant System Including Analysis of Hysteresis Loop
192 -- 0Jon C. Strauss. R68-6 Regression Analysis and Parameter Identification

Volume 17, Issue 12

1121 -- 1131Wolfgang Giloi, Hartmut Grebe. Construction of Multistep Integration Formulas for Simulation Purposes
1131 -- 1143Glen G. Langdon Jr.. Analysis of Asynchronous Circuits Under Different Delay Assumptions
1144 -- 1151Leo Hellerman, Gerhard E. Hoernes. Control Storage Use in Implementing an Associative Memory for a Time-Shared Processor
1151 -- 1156John E. Gaffney Jr.. Sequential Decision-Making Device for Information-Processing Applications
1157 -- 1164William G. Wee. Generalized Inverse Approach to Adaptive Multiclass Pattern Classification
1165 -- 1172James A. Cadzow. Synthesis of Nonlinear Decision Boundaries by Cascaded Threshold Gates
1173 -- 1174M. Silverberg. Near-Optimal Ordering of Electronic Circuit Equations
1175 -- 1176Héctor Arango, Jorge Santos, Alicia Chacur. Ternary Cyclo-Decompositions
1179 -- 1181George Hannauer. R68-51 The Design of an Automatic Patching System
1181 -- 1182W. R. Sutherland. R68-53 A System for Interactive Graphical Programming
1181 -- 0Codie Wells. R68-52 The Structure of the "The"-Multiprogramming System

Volume 17, Issue 11

1027 -- 1037Frank A. Russo, Robert J. Valek. Process Performance Computer for Adaptive Control Systems
1037 -- 1043Robert H. Mitchell, Thomas Williams, William D. Ryan. A Delay Line and Logic Circuits Utilizing Charge-Storage Subharmonic Parametric Oscillators
1044 -- 1061Giovanni B. Gerace. Digital System Design Automation - A Method for Designing a Digital System as a Sequential Network System
1062 -- 1065Sigurd Waaben. High-Speed, Interlaced WRITE and READ-Only Operation of a Plated-Wire Memory System
1066 -- 1073Akio Sasaki. The Basis for Implementation of Ad idive Operations in the Residue Number System
1074 -- 1080Giuseppe Fantauzzi. NORNAND Maitra Cascades
1081 -- 1088Yao Tung Yen. Some Theoretical Properties of Multithreshold Realizable Functions
1089 -- 0Albert W. Small. Partitions and Edge-Weighted Pair-Graphs
1090 -- 0M. G. Harman. An Attempt to Design an Improved Multiplication System
1091 -- 1092Edward S. Davidson, Gernot Metze. Comments on "An Algorithm for Synthesis of Multiple-Output Combinational Logic"
1093 -- 1095Edward G. Coffman Jr., Martin S. Schmookler. A Random-Walk Model of a Queue Storage Problem
1098 -- 0Jay Earley. R68-46 Use of Transition Matrices in Compiling
1098 -- 1099D. W. Fife. R68-47 Computer Scheduling Methods and Their Countermeasures
1099 -- 0William M. Newman. R68-48 A Multiprogramming Monitor for Small Machines
1099 -- 0W. C. McGee. R68-49 Virtual Memory Processes and Sharing in Multics
1100 -- 0Charles L. Jackson. R68-50 Multiprogramming System Performance Measurement and Analysis

Volume 17, Issue 10

925 -- 934Damiel E. Atkins. Higher-Radix Division Using Estimates of the Divisor and Partial Remainders
935 -- 943Mu-Yue Hsiao. Single-Channel Error Correction in an f-Channel System
943 -- 949John L. Shanks, Thomas W. Cairns. Use of a Digital Convolution Device to Perform Recursive Filtering and the Cooley-Tukey Algorithm
949 -- 953Edward A. Patrick, Douglas R. Anderson, F. K. Bechtel. Mapping Multidimensional Space to One Dimension for Computer Output Display
954 -- 965David L. Johnson, Kenneth Herbert O'Keefe. The Application of Shift Registers to Secondary State Assignment: Part I
966 -- 977David L. Johnson, Kenneth Herbert O'Keefe. The Application of Shift Registers to Secondary State Assignment: Part II
978 -- 985Nicolae N. Necula. An Algorithm for Multithreshold Threshold Element Synthesis
986 -- 987L. K. Wadhwa. Simulation of Nonquiescent Third-Order Systems by a Single Operational Amplifier
987 -- 989Chi-hau Chen. Computer Processing of Radiation Sensor PCM Data
990 -- 992Herbert D. Goldman, J. Rom. Considering Solder Connections, Does Triplicated Majority Voting Apply to Integrated Circuits
992 -- 997N. Kouvaras, D. Lagoyannis, L. Ponticopoulos. A Digital System of Simultaneous Addition of Several Binary Numbers
997 -- 998Donald R. Haring. A Technique for Improving the Reliability of Certain Classes of Threshold Elements
1003 -- 0Celso de Renna e Souza. R 68-44 Mathematical Logic
1004 -- 0W. A. Farrand. R68-45 Electrically Alterable Digital Differential Analyzer

Volume 17, Issue 1

2 -- 9Joel N. Sturman. An Iteratively Structured General-Purpose Digital Computer
10 -- 17Joel N. Sturman. Asynchronous Operation of an Iteratively Structured General-Purpose Digital Computer
18 -- 26Janusz A. Brzozowski, Shanker Singh. Definite Asynchronous Sequential Circuits
27 -- 31Florin Stuanciulescu, Mihai Francisc Anton Oprescu. A Mathematical Model of Finite Random Sequential Automata
32 -- 46Chao-Wei Mow, King-sun Fu. An Approach for the Realization of Multithreshold Threshold Elements
46 -- 54Chao-Wei Mow, King-sun Fu. Input Tolerance Considerations for Multithreshold Threshold Elements
54 -- 55Kenneth H. Konkle. An Analog Comparator as a Pseudo-Light Pen for Computer Displays
55 -- 57Michael A. Harrison. On Equivalence of State Assignments
57 -- 66Chao-Wei Mow, King-sun Fu. Generation of Self-Dual and Self-Complementary Dual Functions
66 -- 67Michael Yoeli. Ternary Cellular Cascades
67 -- 71Monroe M. Newborn. Maximal Memory Binary Input-Binary Output Finite-Memory Sequential Machines
72 -- 75David R. Smith. A Partitioning Method for Combinational Synthesis
75 -- 78Robert O. Winder. Symmetry Types in Threshold Logic
78 -- 81John R. Smith, Cyrus O. Harbourt. An Adaptive Threshold Logic Gate Using Capacitive Analog Weights
81 -- 84R. Jeffrey Leake, H. L. Althaus. DDA Scaling Graph
84 -- 86Kenneth C. Knowlton. A Combination Hardware-Software Debugging System
86 -- 89Edward G. Coffman Jr.. A Simple Probability Model Yielding Performance Bounds for Modular Memory Systems
89 -- 94J. P. Seddon, R. A. Johnson. The Simulation of Variable Delay
94 -- 95W. Fred Cutlip. On the Cascade Decomposition of Prefix Automata
95 -- 0Suresh Chander. On Dolotta-McCluskey Technique