| 457 | -- | 460 | Charles R. Kime. Fault Tolerant Computing: An Introduction and a Perspective |
| 468 | -- | 475 | John F. Meyer, Robert J. Sundstrom. On-Line Diagnosis of Unrestricted Faults |
| 476 | -- | 482 | Francisco J. O. Dias. Fault Masking in Combinational Logic Circuits |
| 483 | -- | 489 | Alan M. Usas. A Totally Self-Checking Checker Design for the Detection of Errors in Periodic Signals |
| 489 | -- | 497 | Norman Benowitz, Donald F. Calhoun, Gary E. Alderson, John E. Bauer, Carl T. Joeckel. An Advanced Fault Isolation System for Digital Logic |
| 498 | -- | 505 | Albert L. Hopkins Jr., T. Basil Smith III. The Architectural Elements of a Symmetric Fault-Tolerant Multiprocessor |
| 505 | -- | 512 | T. Basil Smith III. A Damage- and Fault-Tolerant Input/Output Network |
| 512 | -- | 516 | Mu Y. Hsiao, Douglas C. Bossen. Orthogonal Latin Square Configuration for LSI Memory Yield and Reliability Enhancement |
| 517 | -- | 525 | Barry R. Borgerson, Richard F. Freitas. A Reliability Model for Gracefully Degrading and Standby-Sparing Systems |
| 525 | -- | 533 | Daniel P. Siewiorek. Reliability Modeling of Compensating Module Failures in Majority Voted Redundancy |
| 534 | -- | 544 | Roy C. Ogus. The Probability of a Correct Output from a Combinational Circuit |
| 545 | -- | 553 | George B. Leeman Jr.. Some Problems in Certifying Microprograms |
| 554 | -- | 560 | William E. Howden. Methodology for the Generation of Program Test Data |
| 560 | -- | 562 | Siu-Chong Si, Alfred K. Susskind. A Method for Obtaining SPOOF s |
| 562 | -- | 567 | Chantal Robach, Gabriele Saucier. Diversified Test Methods for Local Control Units |
| 567 | -- | 570 | Dwight H. Sawin III. Design of Reliable Synchronous Sequential Circuits |
| 570 | -- | 573 | John F. Wakerly. Transient Failures in Triple Modular Redundancy Systems with Sequential Modules |
| 573 | -- | 578 | Kenneth P. Parker, Edward J. McCluskey. Analysis of Logic Circuits with Faults Using Input Signal Probabilities |
| 578 | -- | 584 | Jacob A. Abraham. A Combinatorial Solution to the Reliability of Interwoven Redundant Logic Networks |