| 129 | -- | 137 | Kang G. Shin, Ming-Syan Chen. Performance Analysis of Distributed Routing Strategies Free of Ping-Pong-Type Looping |
| 138 | -- | 146 | Imrich Chlamtac, Ora Ganz. Performance Models of Asynchronous Multitrunk HYPERchannel Networks |
| 147 | -- | 156 | Hsieh S. Hou. The Fast Hartley Transform Algorithm |
| 157 | -- | 166 | Hung Chi Lai, Saburo Muroga. Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of ::::n:::: Variables |
| 167 | -- | 174 | Patricia J. Eberlein. On the Schur Decomposition of a Matrix for Parallel Computation |
| 175 | -- | 184 | Lee D. Coraor, Paul T. Hulina, Orlando A. Morean. A General Model for Memory-Based Finite-State Machines |
| 185 | -- | 200 | Kostas N. Oikonomou. Abstractions of Finite-State Machines Optimal with Respect to Single Undetectable Output Faults |
| 201 | -- | 211 | Sudhakar M. Reddy, Dong Sam Ha. A New Approach to the Design of Testable PLA s |
| 212 | -- | 214 | Agnes Hui Chan. Using Decision Trees to Derive the Complement of a Binary Function with Multiple-Valued Inputs |
| 215 | -- | 226 | Mark G. Karpovsky. Multilevel Logical Networks |
| 226 | -- | 230 | Keijiro Nakamura. Inverter-Minimum Networks |
| 231 | -- | 233 | Roger W. Hockney. Algorithmic Phase Diagrams |
| 233 | -- | 239 | Harry A. G. Wijshoff, Jan van Leeuwen. On Linear Skewing Schemes and d-Ordered Vectors |
| 239 | -- | 240 | . On the Time-Bandwidth Proof in VLSI Complexity |
| 241 | -- | 247 | Alan A. Bertossi, Maurizio A. Bonuccelli. A VLSI Implementation of the Simplex Algorithm |
| 247 | -- | 250 | Harold Fleisher, Morton Tavel, John Yeager. A Computer Algorithm for Minimizing Reed-Muller Canonical Forms |
| 250 | -- | 252 | Wenlong Zhang, Jack K. Wolf. Rate 1/2 and 2/3 Majority Logic Decodable Binary Burst Error-Correcting Codes |
| 252 | -- | 256 | Cary K. Chin, Edward J. McCluskey. Test Length for Pseudorandom Testing |