Journal: IEEE Transactions on Computers

Volume 36, Issue 9

1009 -- 1018Dan Gordon. Efficient Embeddings of Binary Trees in VLSI Arrays
1019 -- 1029Michael Granski, Israel Koren, Gabriel M. Silberman. The Effect of Operation Scheduling on the Performance of a Data Flow Computer
1030 -- 1040C. Mani Krishna, Kang G. Shin, Inderpal S. Bhandari. Processor Tradeoffs in Distributed Real-Time Systems
1041 -- 1051Victor O. K. Li. Performance Models of Timestamp-Ordering Concurrency Control Algorithms in Distributed Databases
1052 -- 1062Menachem Berg, Israel Koren. On Switching Policies for Modular Redundancy Fault-Tolerant Computing Systems
1063 -- 1075Alan Jay Smith. Line (Block) Size Choice for CPU Cache Memories
1076 -- 1087Hidenori Umeno, Shunji Tanaka. New Methods for Realizing Plural Near-Native Performance Virtual Machines
1088 -- 1096Eberhard Lange. Implementation and Test of the ACRITH Facility in a System/370
1097 -- 1101Micaela Serra, Jon C. Muzio. Testing Programmable Logic Arrays by Sum of Syndromes
1101 -- 1107Rami G. Melhem. A Study of Data Interlock in Computational Networks for Sparse Matrix Multiplication
1107 -- 1212Mandyam M. Srinivasan. Successively Improving Bounds on Performance Measures for Single Class Product Form Queueing Networks
1112 -- 1114Balakrishnan Krishnamurthy. Constructing Test Cases for Partitioning Heuristics
1114 -- 1120Jan Gecsei, Eduard Cerny. Self-Adjusting Networks for VLSI Simulation
1121 -- 1123Takashi Nanya, Toshiaki Kawamura. A Note on Strongly Fault-Secure Sequential Circuits
1123 -- 1128Robert I. Damper, N. Burgess. MOS Test Pattern Generation Using Path Algebras
1128 -- 1132Steven S. Liu, Q. C. Chow. Performance Analysis of a Multiprocessor-Based Packet Switch in Networks with Link-Level Sliding-Window Flow Control
1132 -- 1135Seiichi Nishihara, Hiroji Nishino. Binary Search Revisited: Another Advantage of Fibonacci Search

Volume 36, Issue 8

904 -- 916Karsten Schwan, Prabha Gopinath, Win Bo. CHAOS-Kernel Support for Objects in the Real-Time Domain
917 -- 932Michael F. Coulas, Glenn H. MacEwen, Genevieve Marquis. RNet: A Hard Real-Time Distributed Programming System
933 -- 940Hermann Kopetz, Wilhelm Ochsenreiter. Clock Synchronization in Distributed Real-Time Systems
941 -- 948Insup Lee, Susan B. Davidson. Adding Time to Synchronous Process Communications
949 -- 960Wei Zhao, Krithi Ramamritham, John A. Stankovic. Preemptive Scheduling Under Time and Resource Constraints
961 -- 975Farnam Jahanian, Aloysius K. Mok. A Graph-Theoretic Approach for Timing Analysis and its Implementation
976 -- 987Yann-Hang Lee, Philip S. Yu, Balakrishna R. Iyer. Progressive Transaction Recovery in Distributed DB/DC Systems
988 -- 993Richard A. Volz, Trevor N. Mudge. Instruction Level Timing Mechanisms for Accurate Real-Time Task Scheduling
993 -- 1000James F. Kurose, Renu Chipalkatti. Load Sharing in Soft Real-Time Distributed Computer Systems
1000 -- 1005Frederic L. Swern, Salvatore J. Bavuso, Anna L. Martensen, Paul S. Miner. The Effects of Latent Faults on Highly Reliable Computer Systems

Volume 36, Issue 7

773 -- 793Bezalel Gavish. Optimization Models for Configuring Distributed Computer Systems
794 -- 801André Seznec. A New Interconnection Network for SIMD Computers: The Sigma Network
802 -- 809A. Yavuz Oruç, M. Yaman Oruç. Programming Cellular Permutation Networks Through Decomposition of Symmetric Groups
810 -- 822Ted H. Szymanski, V. Carl Hamacher. On the Permutation Capability of Multistage Interconnection Networks
823 -- 844Svetlana P. Kartashev, Steven I. Kartashev. Analysis and Synthesis of Dynamic Multicomputer Networks that Reconfigure into Rings, Trees, and Stars
845 -- 858Daniel A. Reed, Loyce M. Adams, Merrell L. Patrick. Stencils and Problem Partitionings: Their Influence on the Performance of Multiple Processor Systems
859 -- 875Philip G. Emma, Edward S. Davidson. Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance
876 -- 884Jung H. Kim, Winser E. Alexander. A Multiprocessor Architecture for Two-Dimensional Digital Filters
885 -- 888Sheldon B. Akers, Balakrishnan Krishnamurthy. On Group Graphs and Their Fault Tolerance
888 -- 891Kunio Fukunaga, Shoichiro Yamada, Tamotsu Kasai. Asignment of Job Modules onto Array Processors
891 -- 895Wu-Tung Cheng, Janak H. Patel. A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders
895 -- 897Milos D. Ercegovac, Tomás Lang. On-the-Fly Conversion of Redundant into Conventional Representations

Volume 36, Issue 6

650 -- 666Takanobu Baba, S. Bing Yao, Alan R. Hevner. Design of a Functionally Distributed, Multiprocessor Database Machine Using Data Flow Analysis
667 -- 679Wesley W. Chu, Lance M.-T. Lan. Task Allocation and Precedence Relations for Distributed Real-Time Systems
680 -- 691Sudhakar Yalamanchili, Jake K. Aggarwal. A Characterization and Analysis of Parallel Processor Interconnection Networks
692 -- 701Theodore K. Apostolopoulos, Efstathios D. Sykas, Emmanuel N. Protonotarios. Analysis of a New Retransmission Control Algorithm for Slotted CSMA/CD LAN s
702 -- 713Miguel Angel Fiol, J. Luis A. Yebra, Ignacio Alegre, Mateo Valero. A Discrete Optimization Problem in Local Networks and Data Alignment
714 -- 727Veljko M. Milutinovic, Noé Lopez-Benitez, Kai Hwang. A GaAs-Based Microprocessor Architecture for Real-Time Applications
728 -- 737Imrich Chlamtac, Shlomit S. Pinter. Distributed Nodes Organization Algorithm for Channel Access in a Multihop Dynamic Radio Network
738 -- 744Ambuj Goyal, Asser N. Tantawi. Evaluation of Performability for Degradable Computer Systems
745 -- 760W. K. Luk, Paolo Sipala, C. K. Wong. Minimum-Area Wiring for Slicing Structures
761 -- 764Yu-cheng Liu, Chi-Jiunn Jou. Effective Memory Bandwidth and Processor Blocking Probability in Multiple-Bus Systems
764 -- 768Jay J. Thomas, Sydney R. Parker. Implementing Exact Calculations in Hardware
768 -- 772Kyungsook Y. Lee. A New Benes Network Control Algorithm

Volume 36, Issue 5

517 -- 528Hemant Kanakia, Fouad A. Tobagi. On Distributed Computations with Limited Resources
529 -- 537Ram Chillarege, Ravishankar K. Iyer. Measurement-Based Analysis of Error Latency
538 -- 546Arun K. Somani, Vinod K. Agarwal, David Avis. A Generalized Theory for System Level Diagnosis
547 -- 553William J. Dally, Charles L. Seitz. Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
554 -- 561Peter J. B. King, Isi Mitrani. Modeling a Slotted Ring Local Area Network
562 -- 569Yaron I. Gold, William R. Franta. A Scheduling-Function-Based Distributed Access Protocol that Uses CDM to Relay Control Information in a Network with Hidden Nodes
570 -- 580Marsha J. Berger, Shahid H. Bokhari. A Partitioning Strategy for Nonuniform Problems on Multiprocessors
581 -- 591Alan Norton, Allan J. Silberger. Parallelization and Performance Analysis of the Cooley-Tukey FFT Algorithm for Shared-Memory Architectures
592 -- 602Jacob Savir, William H. McAnney, Salvatore R. Vecchio. Fault Propagation Through Embedded Multiport Memories
603 -- 614Sun-Yuan Kung, Sheng-Chun Lo, Paul S. Lewis. Optimal Systolic Design for the Transitive Closure and the Shortest Path Problems
615 -- 619Lamine Melkemi, Maurice Tchuente. Complexity of Matrix Product on a Class of Orthogonally Connectid Systolic Arrays
619 -- 623Abhijit Sengupta, Arunabha Sen, Subir Bandyopadhyay. On an Optimally Fault-Tolerant Multiprocessor Network Architecture
623 -- 629Frantisek Kremla. General Criterion for Essential Nonfault Locatability of Logical Functions
629 -- 634Stanislaw J. Piestrak. Design of Fast Self-Testing Checkers for a Class of Berger Codes
634 -- 637Asish Mukhopadhyay. A Solution to the Polynomial Hensel Code Conversion Problem
637 -- 640Chun-Fu Huang, Wen-Tsuen Chen. Fault-Tolerant Single-Stage Interconnection Networks
640 -- 644Carla Neaderhouser Purdy, George B. Purdy. Integer Division in Linear Time with Bounded Fan-In

Volume 36, Issue 4

388 -- 395Pen-Chung Yew, Nian-Feng Tzeng, Duncan H. Lawrie. Distributing Hot-Spot Addressing in Large-Scale Multiprocessors
396 -- 409Ronald P. Bianchini Jr., John Paul Shen. Interprocessor Traffic Scheduling Algorithm for Multiple-Processor Networks
410 -- 420Constantine D. Polychronopoulos, Utpal Banerjee. Processor Allocation for Horizontal and Vertical Parallelism and Related Speedup Bounds
421 -- 432Zarka Cvetanovic. The Effects of Problem Partitioning, Allocation, and Granularity on the Performance of Multiple-Processor Systems
433 -- 442Soo-Young Lee, J. K. Aggarwal. A Mapping Strategy for Parallel Processing
443 -- 448Maurice Herlihy. Extending Multiversion Time-Stamping Protocols to Exploit Type Information
449 -- 459Richard A. Volz, Trevor N. Mudge. Timing Issues in the Distributed Execution of Ada Programs
460 -- 470Kshitij Doshi, Peter J. Varman. Optimal Graph Algorithms on a Fixed-Size Linear Array
471 -- 482Thomas J. LeBlanc, John M. Mellor-Crummey. Debugging Parallel Programs with Instant Replay
483 -- 499Ahmed E. Kamal. Star Local Area Networks: A Performance Study
500 -- 516Dar-Tzen Peng, Kang G. Shin. Modeling of Concurrent Task Execution in a Distributed System for Real-Time Control

Volume 36, Issue 3

257 -- 263Gardiner S. Stiles, Dong-Lih Denq. A Quantitative Comparison of the Performance of Three Discrete Distributed Associative Memory Models
264 -- 276Michael A. Schuette, John Paul Shen. Processor Control Flow Monitoring Using Signatured Instruction Streams
277 -- 292Robert Brian Cutler, Saburo Muroga. Derivation of Minimal Sums for Completely Specified Functions
293 -- 298David H. Bailey. Vector Computer Memory Bank Contention
299 -- 311Louis G. Birta, Osman Abou-Rabia. Parallel Block Predictor-Corrector Methods for ode s
312 -- 320David Hung-Chang Du, Lee-Chin Hsu Liu. Heuristic Algorithms for Single Row Routing
321 -- 331Ying-Fung Wu, Peter Widmayer, Martine D. F. Schlag, C. K. Wong. Rectilinear Shortest Paths and Minimum Spanning Trees in the Presence of Rectilinear Obstacles
332 -- 343Kenneth D. Wagner, Cary K. Chin, Edward J. McCluskey. Pseudorandom Testing
344 -- 355Israel Koren, Dhiraj K. Pradhan. Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems
356 -- 359Y. S. Kuo. Generating Essential Primes for a Boolean Function with Multiple-Valued Inputs
359 -- 362Albert G. Greenberg, Udi Manber. A Probabilistic Pipeline Algorithm for ::::K:::: Selection on the Tree Machine
365 -- 369Pinaki Mazumder. Evaluation of On-Chip Static Interconnection Networks
369 -- 373Robert P. Treuer, Vinod K. Agarwal, Hideo Fujiwara. A New Built-In Self-Test Design for PLA s with High Fault Coverage and Low Overhead
373 -- 378Anton T. Dahbura, Krishan K. Sabnani, Linda L. King. The Comparison Approach to Multiprocessor Fault Diagnosis
378 -- 383Che-Liang Yang, Gerald M. Masson. A New Measure for Hybrid Fault Diagnosability
383 -- 384Frank K. Hwang. Comments on Reliable Loop Topologies for Large Local Computer Networks

Volume 36, Issue 2

129 -- 137Kang G. Shin, Ming-Syan Chen. Performance Analysis of Distributed Routing Strategies Free of Ping-Pong-Type Looping
138 -- 146Imrich Chlamtac, Ora Ganz. Performance Models of Asynchronous Multitrunk HYPERchannel Networks
147 -- 156Hsieh S. Hou. The Fast Hartley Transform Algorithm
157 -- 166Hung Chi Lai, Saburo Muroga. Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of ::::n:::: Variables
167 -- 174Patricia J. Eberlein. On the Schur Decomposition of a Matrix for Parallel Computation
175 -- 184Lee D. Coraor, Paul T. Hulina, Orlando A. Morean. A General Model for Memory-Based Finite-State Machines
185 -- 200Kostas N. Oikonomou. Abstractions of Finite-State Machines Optimal with Respect to Single Undetectable Output Faults
201 -- 211Sudhakar M. Reddy, Dong Sam Ha. A New Approach to the Design of Testable PLA s
212 -- 214Agnes Hui Chan. Using Decision Trees to Derive the Complement of a Binary Function with Multiple-Valued Inputs
215 -- 226Mark G. Karpovsky. Multilevel Logical Networks
226 -- 230Keijiro Nakamura. Inverter-Minimum Networks
231 -- 233Roger W. Hockney. Algorithmic Phase Diagrams
233 -- 239Harry A. G. Wijshoff, Jan van Leeuwen. On Linear Skewing Schemes and d-Ordered Vectors
239 -- 240. On the Time-Bandwidth Proof in VLSI Complexity
241 -- 247Alan A. Bertossi, Maurizio A. Bonuccelli. A VLSI Implementation of the Simplex Algorithm
247 -- 250Harold Fleisher, Morton Tavel, John Yeager. A Computer Algorithm for Minimizing Reed-Muller Canonical Forms
250 -- 252Wenlong Zhang, Jack K. Wolf. Rate 1/2 and 2/3 Majority Logic Decodable Binary Burst Error-Correcting Codes
252 -- 256Cary K. Chin, Edward J. McCluskey. Test Length for Pseudorandom Testing

Volume 36, Issue 12

1396 -- 1407Ming-Syan Chen, Kang G. Shin. Processor Allocation in an ::::N::::-Cube Multiprocessor Using Gray Codes
1408 -- 1424P. Sadayappan, Fikret Erçal. Nearest-Neighbor Mapping of Finite Element Graphs onto Processor Meshes
1425 -- 1439Constantine D. Polychronopoulos, David J. Kuck. Guided Self-Scheduling: A Practical Scheduling Scheme for Parallel Supercomputers
1440 -- 1449David T. Harper III, J. Robert Jump. Vector Access Performance in Parallel Memories Using a Skewed Storage Scheme
1450 -- 1466Kai Hwang, Joydeep Ghosh. Hypernet: A Communication-Efficient Architecture for Constructing Massively Parallel Computers
1467 -- 1484Stanley Y. W. Su, Arun K. Thakore. Matrix Operations on a Multicomputer System with Switchabel Main Memory Modules and Dynamic Control
1485 -- 1495Samuel P. Midkiff, David A. Padua. Compiler Algorithms for Synchronization
1496 -- 1514Wen-mei W. Hwu, Yale N. Patt. Checkpoint Repair for High-Performance Out-of-Order Execution Machines
1515 -- 1522Richard Buehrer, Kattamuri Ekanadham. Incorporating Data Flow Ideas into von Neumann Processors for Parallel Execution
1523 -- 1538Marco Annaratone, Emmanuel A. Arnould, Thomas R. Gross, H. T. Kung, Monica S. Lam, Onat Menzilcioglu, Jon A. Webb. The Warp Computer: Architecture, Implementation, and Performance

Volume 36, Issue 11

1265 -- 1274Izidor Gertner, Moshe Shamash. VLSI Architectures for Multidimensional Fourier Transform Processing
1275 -- 1291Edmund H. Durfee, Victor R. Lesser, Daniel D. Corkill. Coherent Cooperation Among Communicating Problem Solvers
1292 -- 1309Stephen F. Lundstrom. Applications Considerations in the System Design of Highly Concurrent Multiprocessors
1310 -- 1317Naofumi Takagi, Shuzo Yajima. On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic
1318 -- 1327Janusz A. Brzozowski, Carl-Johan H. Seger. A Characterization of Ternary Simulation of Gate Networks
1328 -- 1341Kang G. Shin, Tein-Hsiang Lin, Yann-Hang Lee. Optimal Checkpointing of Real-Time Tasks
1342 -- 1348Robert Michael Owens, Mary Jane Irwin. The Arithmetic Cube
1349 -- 1354Bernard Chazelle, Herbert Edelsbrunner. An Improved Algorithm for Constructing ::::k:::: th-Order Voronoi Diagrams
1355 -- 1359Dianne P. O Leary, G. W. Stewart. From Determinacy to Systaltic Arrays
1359 -- 1363Robert H. Deng, Daniel J. Costello Jr.. Decoding of DBEC-TBED Reed-Solomon Codes
1363 -- 1367Hao-Yung Lo, Jau-Ling Chen. A Hardwired Generalized Algorithm for Generating the Logarithm Base-::::k:::: by Iteration
1367 -- 1369Selim G. Akl, Nicola Santoro. Optimal Parallel Merging and Sorting Without Memory Conflicts
1369 -- 1374Che-Liang Yang, Gerald M. Masson. A Generalization of Hybrid Fault Diagnosability
1374 -- 1378R. Conterno, Riccardo Melen. An Analytical Model for a Class of Processor-Memory Interconnection Networks
1378 -- 1382Seyed H. Hosseini, Jon G. Kuhl, Sudhakar M. Reddy. Distributed Fault-Tolerance of Tree Structures
1382 -- 1386Mohammad Ilyas, H. T. Mouftah. End-to-End Flow Control in Computer Networks with Noisy Channels and Quasi-Cut-Through Switching
1387 -- 1389Chwan-Chia Wu. Time Redundant Fault-Location in Bit-Sliced ALU's
1389 -- 1392Takashi Nanya, Toshiaki Kawamura. On Error Indication for Totally Self-Checking Systems

Volume 36, Issue 10

1137 -- 1143Adly T. Fam. Optimal Partitioning and Redundancy Removal in Computing Partial Sums
1144 -- 1152Alain Guyot, Bertrand Hochet, Jean-Michel Muller. A Way to Build Efficient Carry-Skip Adders
1153 -- 1164Clement T. Yu, Keh-Chang Guh, Weining Zhang, Marjorie Templeton, David Brill, Arbee L. P. Chen. Algorithms to Process Distributed Queries in Fast Local Networks
1165 -- 1171Hirokazu Okano, Hideki Imai. A Construction Method of High-Speed Decoders Using ROMS s for Bose-Chaudhuri-Hocquenghem and Reed-Solomon Codes
1172 -- 1182Matthew B. Lowrie, W. Kent Fuchs. Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance
1183 -- 1196Kathleen M. Nichols, David G. Messerschmitt. Traffic-Specific Interconnection Networks for Multicomputers
1197 -- 1208Daniel Barbará, Hector Garcia-Molina. The Reliability of Voting Mechanisms
1209 -- 1223Imrich Chlamtac, Shay Kutten. Tree-Based Broadcasting in Multihop Radio Networks
1224 -- 1232Salim Hariri, Cauligi S. Raghavendra. SYREL: A Symbolic Reliability Algorithm Based on Path and Cutset Methods
1233 -- 1236Behrooz Parhami. On the Complexity of Table Lookup for Iterative Division
1236 -- 1242G. Robert Redinbo. Finite Field Fault-Tolerant Digital Filtering Architectures
1243 -- 1247I-Chen Wu. A Fast 1-D Serial-Parallel Systolic Multiplier
1247 -- 1251George Markowsky. Bounding Signal Probabilities in Combinational Circuits
1251 -- 1255Daniel M. Chapiro. Reliable High-Speed Arbitration and Synchronization
1255 -- 1258Hsuen-Chyun Shyu, Trieu-Kien Truong, Irving S. Reed. A Complex Integer Multiplier Using the Quadratic-Polynomial Residue Number System with Numbers of Form 2:::::::2n::::::: + 1
1258 -- 1263Baruch Awerbuch, Yossi Shiloach. New Connectivity and MSF Algorithms for Shuffle-Exchange Network and PRAM

Volume 36, Issue 1

2 -- 12Kang G. Shin, Parameswaran Ramanathan. Clock Synchronization of a Large Multiprocessor System in the Presence of Malicious Faults
13 -- 23John H. Zurawski, J. B. Gosling. Design of a High-Speed Square Root Multiply and Divide Unit
24 -- 35Edward A. Lee, David G. Messerschmitt. Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing
36 -- 46Richard J. Zaccone, Jesse L. Barlow. Eliminating the Normalization Problem in Digit On-Line Arithmetic
47 -- 63G. Robert Redinbo. Fault-Tolerant Decoders for Cyclic Error-Correcting Codes
64 -- 75Jik H. Chang, Oscar H. Ibarra, Michael A. Palis. Parallel Parsing on a One-Way Array of Finite-State Machines
76 -- 85Mark A. Holliday, Mary K. Vernon. Exact Performance Estimates for Multiprocessor Memory and Bus Interference
86 -- 93Eiji Fujiwara, Kohji Matsuoka. A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing
94 -- 99John P. Robinson, Nirmal R. Saxena. A Unified View of Test Compression Methods
100 -- 105Alan M. Schwartz, Michael C. Loui. Dictionary Machines on Cube-Class Networks
105 -- 109Zhiyuan Li, Walid A. Abu-Sufah. On Reducing Data Synchronization in Multiprocessed Loops
109 -- 112Lindsay Kleeman, Antonio Cantoni. On the Unavoidability of Metastable Behavior in Digital Systems
112 -- 117. (lambda, ::::T::::) Complexity Measures for VLSI Computations in Constant Chip Area
117 -- 122Dianne P. O Leary. Systolic Arrays for Matrix Transpose and Other Reorderings
122 -- 125Ian F. Akyildiz. Exact Product Form Solution for Queueing Networks with Blocking