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Journal: IEEE Trans. on CAD of Integrated Circuits and Systems
Home
Index
Info
Issue
Volume
11
, Issue
12
1469
--
1478
Carl Pixley
.
A theory and implementation of sequential hardware equivalence
1479
--
1494
Richard W. Thaik
,
Ngee Lek
,
Sung-Mo Kang
.
A new global router using zero-one integer linear programming techniques for sea-of-gates and custom logic arrays
1495
--
1507
Jin-fuw Lee
,
Chak-Kuen Wong
.
A performance-aimed cell compactor with automatic jogs
1508
--
1521
Shan-Ping Chin
,
Ching-Yuan Wu
.
A new methodology for two-dimensional numerical simulation of semiconductor devices
1522
--
1528
H.-C. Chow
,
W.-S. Feng
,
James B. Kuo
.
An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation
1529
--
1558
Shiu-Kai Chin
.
Verified functions for generating signed-binary arithmetic hardware
1559
--
1573
Srinivas Devadas
,
Kurt Keutzer
.
Validatable nonrobust delay-fault testable circuits via logic synthesis
1574
--
1585
Raja Venkateswaran
,
Pinaki Mazumder
,
K. G. Shin
.
Restructuring WSI hexagonal processor arrays