Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

Volume 11, Issue 12

1469 -- 1478Carl Pixley. A theory and implementation of sequential hardware equivalence
1479 -- 1494Richard W. Thaik, Ngee Lek, Sung-Mo Kang. A new global router using zero-one integer linear programming techniques for sea-of-gates and custom logic arrays
1495 -- 1507Jin-fuw Lee, Chak-Kuen Wong. A performance-aimed cell compactor with automatic jogs
1508 -- 1521Shan-Ping Chin, Ching-Yuan Wu. A new methodology for two-dimensional numerical simulation of semiconductor devices
1522 -- 1528H.-C. Chow, W.-S. Feng, James B. Kuo. An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation
1529 -- 1558Shiu-Kai Chin. Verified functions for generating signed-binary arithmetic hardware
1559 -- 1573Srinivas Devadas, Kurt Keutzer. Validatable nonrobust delay-fault testable circuits via logic synthesis
1574 -- 1585Raja Venkateswaran, Pinaki Mazumder, K. G. Shin. Restructuring WSI hexagonal processor arrays