| 1325 | -- | 1333 | Thang Nguyen Bui, Willie Hsu, SingLing Lee. A 2.5 approximation algorithm for the multi-via assignment problem |
| 1334 | -- | 1343 | Ze-Yi Wang, Ke-Chih Wu, Robert W. Dutton. An approach to construct pre-conditioning matrices for block iteration of linear equations |
| 1344 | -- | 1354 | Carlos H. Díaz, Sung-Mo Kang. New algorithms for circuit simulation of device breakdown |
| 1355 | -- | 1362 | Gerard A. Allan, Anthony J. Walton, Robert J. Holwill. A yield improvement technique for IC layout using local design rules |
| 1363 | -- | 1371 | Tom Chanak, Rakesh Chadha, Kishore Singhal. Switched-capacitor simulation models for full-chips verification |
| 1372 | -- | 1387 | Colin Gordon, Thomas Blazeck, Raj Mittra. Time-domain simulation of multiconductor transmission lines with frequency-dependent losses |
| 1388 | -- | 1401 | Cheryl Harkness, Daniel P. Lopresti. Interval methods for modeling uncertainty in RC timing analysis |
| 1402 | -- | 1417 | J. Paul Harvey, Mohamed I. Elmasry, Bosco Leung. STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits |
| 1418 | -- | 1425 | James A. Power, W. A. Lane. An enhanced SPICE MOSFET model suitable for analog applications |
| 1426 | -- | 1438 | Peter Vanbekbergen, Gert Goossens, Francky Catthoor, Hugo De Man. Optimized synthesis of asynchronous control circuits from graph-theoretic specifications |
| 1439 | -- | 1449 | Vijay S. Iyengar, Gopalakrishnan Vijayan. Optimized test application timing for AC test |
| 1450 | -- | 1458 | Michel Renovell, Gaston Cambon. Electrical analysis and modeling of floating-gate fault |
| 1459 | -- | 1462 | Michele Favalli, Piero Olivo, Bruno Riccò. A probabilistic fault model for analog faults in digital CMOS circuits |
| 1462 | -- | 1465 | Andrew B. Kahng, Gabriel Robins. On the performance bounds for a class of rectilinear Steiner tree heuristics in arbitrary dimension |