| 4 | -- | 15 | Tracy Larrabee. Test pattern generation using Boolean satisfiability |
| 16 | -- | 25 | Dhiren Xavier, Robert C. Aitken, André Ivanov, Vinod K. Agarwal. Using an asymmetric error model to study aliasing in signature analysis registers |
| 26 | -- | 33 | Hans-Joachim Wunderlich, Sybille Hellebrand. The pseudoexhaustive test of sequential circuits |
| 34 | -- | 44 | Thomas M. Sarfert, Remo G. Markgraf, Michael H. Schulz, Erwin Trischler. A hierarchical test pattern generation system based on high-level primitives |
| 45 | -- | 67 | John D. Calhoun, Franc Brglez. A framework and method for hierarchical test generation |
| 68 | -- | 75 | W. David Ballew, Lauren M. Streb. Board-level boundary scan: regaining observability with an additional IC |
| 76 | -- | 82 | David L. Landis. A test methodology for wafer scale system |
| 83 | -- | 86 | Paul H. Bardell. Calculating the effects of linear dependencies in m-sequences used as test stimuli |
| 87 | -- | 101 | Srinivas Devadas, Kurt Keutzer. Synthesis of robust delay-fault-testable circuits: theory |
| 102 | -- | 114 | Lawrence L. Larmore, Daniel D. Gajski, Allen C.-H. Wu. Layout placement for sliced architecture |
| 115 | -- | 127 | Chung-Kuan Cheng, David N. Deutsch, Craig Shohara, Mark Taparauskas, Mark Bubien. Geometric compaction on channel routing |
| 128 | -- | 136 | Gerd Nanz, Peter Dickinger, Siegfried Selberherr. Calculation of contact currents in device simulation |