| 413 | -- | 423 | Stefaan Note, Francky Catthoor, Gert Goossens, Hugo De Man. Combined hardware selection and pipelining in high-performance data-path design |
| 424 | -- | 431 | Thomas F. Hayes, John J. Barrett. Modeling of multiconductor systems for packaging and interconnecting high-speed digital IC s |
| 432 | -- | 442 | Eugene Z. Xia, Resve A. Saleh. Parallel waveform-Newton algorithms for circuit simulation |
| 443 | -- | 452 | Eduard Cerny, John P. Hayes, Nicholas C. Rumin. Accuracy of magnitude-class calculations in switch-level modeling |
| 453 | -- | 463 | Allen C.-H. Wu, Daniel D. Gajski. Partitioning algorithms for layout synthesis from register-transfer netlists |
| 464 | -- | 474 | Nobuo Funabiki, Yoshiyasu Takefuji. A parallel algorithm for channel routing problems [VLSI] |
| 475 | -- | 486 | Chung-Kuan Cheng, Ximtie Deng, Yuh-Zen Liao, So-Zen Yao. Symbolic layout compaction under conditional design rules |
| 487 | -- | 496 | Walter B. Richardson, Graham F. Carey, Brian J. Mulvaney. Modeling phosphorus diffusion in three dimensions |
| 497 | -- | 504 | Zeyi Wang, Qiming Wu. A two-dimensional resistance simulator using the boundary element method |
| 505 | -- | 512 | Keith R. Green, Jerry G. Fossum. A pragmatic approach to integrated process/device/circuit simulation for IC technology development |
| 513 | -- | 524 | George L. Matthaei, Gilbert C. Chinn, Charles H. Plott, Nadir Dagli. A simplified means for computation for interconnect distributed capacitances and inductances |
| 525 | -- | 540 | Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao, Michael Nicolaidis. An SFS Berger check prediction ALU and its application to self-checking processor designs |