Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

Volume 11, Issue 9

1053 -- 1064Fur-Shing Tsai, Yu-Chin Hsu. STAR: An automatic data path allocator
1065 -- 1073Kwang-Ting Cheng, Jing-Yang Jou. A functional fault model for sequential machines
1074 -- 1085Lars W. Hagen, Andrew B. Kahng. New spectral methods for ratio cut partitioning and clustering
1086 -- 1094Xiaodong Zhang. Dynamic and static load balancing for solving block bordered circuit equations on multiprocessors
1095 -- 1103Majid Sarrafzadeh, Chak-Kuen Wong. Hierarchical Steiner tree construction in uniform orientations
1104 -- 1113Tsuneo Okubo, Takashi Watanabe, Kou Wada, Kazuyuki Saito. A novel geometric resizing technique for data conversion from CAD data to electron beam exposure data
1114 -- 1119Masayoshi Shirahata, Hiromi Kusano, Norihiko Kotani, Shigeru Kusanoki, Yoichi Akasaka. A mobility model including the screening effect in MOS inversion layer
1120 -- 1130Peter M. Maurer. Two new techniques for unit-delay compiled simulation
1131 -- 1139. An incremental zero/integer delay switch-level simulation environment
1140 -- 1152Mark Hirsch, Daniel P. Siewiorek. The effect of placement of automatically extracted structure
1153 -- 1160Weiping Shi, W. Kent Fuchs. Probabilistic analysis and algorithms for reconfiguration of memory arrays
1161 -- 1166Wu-Tung Cheng, James L. Lewandowski, Eleanor Wu. Optimal diagnostic methods for wiring interconnects
1166 -- 1172Abhijit Ghosh, Srinivas Devadas, A. Richard Newton. Heuristic minimization of Boolean relations using testing techniques