545 | -- | 554 | TingTing Hwang, Robert Michael Owens, Mary Jane Irwin. Efficiently computing communication complexity for multilevel logic synthesis |
555 | -- | 565 | David M. Lewis. A compiled-code hardware accelerator for circuit simulation |
566 | -- | 574 | Luis Miguel Silveira, Jacob K. White, Horácio C. Neto, Luís M. Vidigal. On exponential fitting for circuit simulation |
575 | -- | 585 | Rakesh Chadha, Chandramouli Visweswariah, Chin-Fu Chen. M:::3:::-a multilevel mixed-mode mixed A/D simulator |
586 | -- | 597 | John Y. Lee, Xiaoli Huang, Ronald A. Rohrer. Pole and zero sensitivity calculation in asymptotic waveform evaluation |
598 | -- | 606 | Donald J. Erdman, Donald J. Rose. Newton waveform relaxation techniques for tightly coupled systems |
607 | -- | 619 | John F. Beetem. Hierarchical topological sorting of apparent loops via partitioning |
620 | -- | 628 | Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic. A detailed router for field-programmable gate arrays |
629 | -- | 637 | John R. F. McMacken, Savvas G. Chamberlain. A numerical model for two-dimensional transient simulation of amorphous silicon thin-film transistors |
638 | -- | 658 | José Pineda de Gyvez, Chennian Di. IC defect sensitivity for footprint-type spot defects |
659 | -- | 670 | Kuen-Jong Lee, Melvin A. Breuer. Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults |
671 | -- | 673 | Deodatta R. Apte, Mark E. Law. Comparison of iterative methods for AC analysis in PISCES-IIB |