| 943 | -- | 954 | Maciej J. Ciesielski, Seiyang Yang. PLADE: a two-stage PLA decomposition |
| 955 | -- | 965 | Rajiv Jain, Alice C. Parker, Nohbyung Park. Predicting system-level area and delay for pipelined and nonpipelined designs |
| 966 | -- | 975 | Albert V. Ferris-Prabhu. On the assumptions contained in semiconductor yield models |
| 976 | -- | 991 | Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng. An H-V alternating router |
| 992 | -- | 1002 | Ting-Chi Wang, Martin D. F. Wong. Optimal floorplan area optimization |
| 1003 | -- | 1012 | Kartikeya Mayaram, Donald O. Pederson. Coupling algorithms for mixed-level circuit and device simulation |
| 1013 | -- | 1023 | Mamoru Kurata, Shin Nakamura. An explicit method of numerical integration for the complete set of semiconductor device equations |
| 1024 | -- | 1031 | Yeong-Yil Yang, Chong-Min Kyung. HALO: an efficient global placement strategy for standard cells |
| 1032 | -- | 1043 | J. Richard Griffith, Michel S. Nakhla. Mixed frequency/time domain analysis of nonlinear circuits |
| 1044 | -- | 1051 | Somchai Prasitjutrakul, William J. Kubitz. A performance-driven global router for custom VLSI chip design |