| 677 | -- | 695 | David W. Knapp. Fasolt: a program for feedback-driven data-path optimization |
| 696 | -- | 718 | David C. Ku, Giovanni De Micheli. Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits |
| 719 | -- | 731 | Yung-Ho Shih, Sung-Mo Kang. Analytic transient solution of general MOS circuit primitives |
| 732 | -- | 738 | Terence B. Hook. Automatic extraction of circuit models from layout artwork for a BiCMOS technology |
| 739 | -- | 752 | Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, Chak-Kuen Wong. Provably good performance-driven global routing |
| 753 | -- | 758 | Charles R. Bonapace, Chi-Yuan Lo. An O(n log m) algorithm for VLSI design rule checking |
| 759 | -- | 767 | Joohyun Jin, Jerry G. Fossum. Non-quasi-static modeling/implementation of BJT current crowding for seminumerical mixed-mode device/circuit simulation |
| 768 | -- | 777 | André Ivanov, Yervant Zorian. Count-based BIST compaction schemes and aliasing probability computation |
| 778 | -- | 793 | Janusz Rajski, Jagadeesh Vasudevamurthy. The testability-preserving concurrent decomposition and factorization of Boolean expressions |
| 794 | -- | 800 | Silvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò. Testability measures in pseudorandom testing |
| 800 | -- | 803 | Michael J. Bryan, Srinivas Devadas, Kurt Keutzer. Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks |