Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

Volume 11, Issue 7

805 -- 815Tom Dhaene, Daniel De Zutter. Selection of lumped element models for coupled lossy transmission lines
816 -- 824Mary L. Bailey. A time-based model for investigating parallel logic-level simulation
825 -- 843Sharad Malik, Luciano Lavagno, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. Symbolic minimization of multilevel logic and the input encoding problem
844 -- 854Sung-Soo Kim, Chong-Min Kyung. Circuit placement on arbitrarily shaped regions using the self-organization principle
855 -- 863Stephan Müller, Kevin Kells, Wolfgang Fichtner. Automatic rectangle-based adaptive mesh generation without obtuse angles
864 -- 875Kenneth M. McDonald, Joseph G. Peters. Smallest paths in simple rectilinear polygons
876 -- 884Hans-Rudolf Heeb, Wolfgang Fichtner. A module generator based on the PQ-tree algorithm
885 -- 892Scott W. Hadley, Brian L. Mark, Anthony Vannelli. An efficient eigenvector approach for finding netlist partitions
893 -- 902Andrew B. Kahng, Gabriel Robins. A new class of iterative Steiner tree heuristics with good performance
903 -- 910Shankar Pennathur, Harry H. L. Kwok. Simulation of charge transfer in GaAs Cermet-Gate CCDs
911 -- 920Edward W. Scheckler, Alexander S. Wong, Robert K. Wang, Goodwin R. Chin, John R. Camagna, Andrew R. Neureuther, Robert W. Dutton. A utility-based integrated system for process simulation
921 -- 925Hiroyoshi Tanimoto, Naoyuki Shigyo. Discretization error in MOSFET device simulation
926 -- 938Eun Sei Park, M. Ray Mercer. An efficient delay test generation system for combinational logic circuits