| 142 | -- | 157 | Bo-Gwan Kim, Donald L. Dietmeyer. Multilevel logic synthesis with extended arrays |
| 158 | -- | 184 | David W. Knapp, Marianne Winslett. A prescriptive formal model for data-path hardware |
| 185 | -- | 197 | Kuochen Wang, Sy-Yen Kuo. Computer-aided modeling and evaluation of reconfigurable VLSI processor arrays with VHDL |
| 198 | -- | 207 | Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel. PROOFS: a fast, memory-efficient sequential circuit fault simulator |
| 208 | -- | 215 | Mary L. Bailey. How circuit size affects parallelism |
| 216 | -- | 227 | Uminder Singh, C. Y. Roger Chen. From logic to symbolic layout for gate matrix |
| 228 | -- | 234 | Takayasu Sakurai, Bill Lin, A. Richard Newton. Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction |
| 235 | -- | 246 | Yusuf Leblebici, Sung-Mo Kang. Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation |
| 247 | -- | 259 | Irith Pomeranz, Zvi Kohavi. A limited exponential complexity algorithm for increasing the testability of digital circuits by testing-module insertion |
| 260 | -- | 267 | Thomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham. Test compaction for sequential circuits |
| 267 | -- | 270 | Xiaoyu Song. An algorithm for L-shaped channel routing in a diagonal model |