| 274 | -- | 295 | Ching-Yi Wang, Keshab K. Parhi. High-level DSP synthesis using concurrent transformations, scheduling, and allocation |
| 296 | -- | 307 | Moon-Jung Chung, Sangchul Kim. A path-oriented algorithm for the cell selection problem |
| 308 | -- | 320 | Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj. Timing and area optimization for standard-cell VLSI circuit design |
| 321 | -- | 336 | Jason Cong, Kwok-Shing Leung. Optimal wiresizing under Elmore delay model |
| 337 | -- | 348 | Wen-Chung Kao, Tai-Ming Parng. Cross point assignment with global rerouting for general-architecture designs |
| 349 | -- | 359 | Wern-Jieh Sun, Carl Sechen. Efficient and effective placement for very large circuits |
| 360 | -- | 370 | Michael M. Green, Alan N. Willson Jr.. An algorithm for identifying unstable operating points using SPICE |
| 371 | -- | 374 | Ching-Dong Chen, Yuh-Sheng Lee, Allen C.-H. Wu, Youn-Long Lin. TRACER-fpga: a router for RAM-based FPGA s |
| 374 | -- | 384 | Wen-Ben Jone, Christos A. Papachristou. A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits |
| 384 | -- | 393 | Ayman I. Kayssi, Karem A. Sakallah. Timing models for gallium arsenide direct-coupled FET logic circuits |
| 393 | -- | 397 | Yu-Wen Tsay, Youn-Long Lin. A row-based cell placement method that utilizes circuit structural properties |