| 1417 | -- | 1436 | Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins. Near-optimal critical sink routing tree constructions |
| 1437 | -- | 1444 | Steven Bova, Graham F. Carey. A Taylor-Galerkin finite element method for the hydrodynamic semiconductor equations |
| 1445 | -- | 1458 | Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta, Melvin A. Breuer. An integrated system for assigning signal flow directions to CMOS transistors |
| 1459 | -- | 1469 | Ivan L. Wemple, Andrew T. Yang. Integrated circuit substrate coupling models based on Voronoi tessellation |
| 1470 | -- | 1479 | K. Fuchs. Synthesis for path delay fault testability via tautology-based untestability identification and factorization |
| 1480 | -- | 1489 | Kamal Chaudhary, Massoud Pedram. Computing the area versus delay trade-off curves in technology mapping |
| 1490 | -- | 1495 | Rajmohan Rajaraman, Martin D. F. Wong. Optimum clustering for delay minimization |
| 1496 | -- | 1504 | Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy. Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits |
| 1505 | -- | 1515 | Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri. NEST: a nonenumerative test generation method for path delay faults in combinational circuits |
| 1516 | -- | 1525 | Ted Stanion, Debashis Bhattacharya, Carl Sechen. An efficient method for generating exhaustive test sets |
| 1526 | -- | 1545 | Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah. Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability |
| 1546 | -- | 1556 | Elizabeth J. Brauer, Sung-Mo Kang. An algorithm for functional verification of digital ECL circuits |
| 1557 | -- | 1568 | Kannan Krishna, Stephen W. Director. The linearized performance penalty (LPP) method for optimization of parametric yield and its reliability |
| 1569 | -- | 1577 | Kurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli. Synthesis for testability techniques for asynchronous circuits |
| 1577 | -- | 1586 | Dhiraj K. Pradhan, Jayashree Saxena. A novel scheme to reduce test application time in circuits with full scan |
| 1586 | -- | 1590 | Alexander Y. Tetelbaum. Generalized optimum path search |