| 531 | -- | 546 | Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy. Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints |
| 547 | -- | 553 | Steffen Tarnick. Controllable self-checking checkers for conditional concurrent checking |
| 554 | -- | 566 | Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer. Test embedding with discrete logarithms |
| 567 | -- | 575 | Siyad C. Ma, Edward J. McCluskey. Open faults in BiCMOS gates |
| 576 | -- | 582 | Wuudiann Ke, Premachandran R. Menon. Path-delay-fault testable nonscan sequential circuits |
| 582 | -- | 590 | Aiman H. El-Maleh, Janusz Rajski. Delay-fault testability preservation of the concurrent decomposition and factorization transformations |
| 590 | -- | 596 | Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell. Fault coverage estimation by test vector sampling |
| 596 | -- | 603 | Terry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs. Circuit-level dictionaries of CMOS bridging faults |
| 603 | -- | 607 | Peter C. Maxwell. Reductions in quality caused by uneven fault coverage of different areas of an integrated circuit |
| 607 | -- | 612 | Vladimir Kolarik, Salvador Mir, Marcelo Lubaszewski, Bernard Courtois. Analog checkers with absolute and relative tolerances |
| 613 | -- | 622 | Yanbing Xu, Mostafa H. Abd-El-Barr, Carl McCrosky. Graph-based output phase assignment for PLA minimization |
| 623 | -- | 630 | Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, T. C. Hu. A replication cut for two-way partitioning |
| 631 | -- | 638 | Masato Fujinaga, I. Tottori, Tatsuya Kunikiyo, Tetsuya Uchida, Norihiko Kotani, Yasumasa Tsukamoto. 3-D numerical modeling of thermal flow for insulating thin film using surface diffusion |
| 639 | -- | 649 | Peter Feldmann, Roland W. Freund. Efficient linear circuit analysis by Pade approximation via the Lanczos process |