| 1183 | -- | 1192 | Bradley S. Carlson, Suh-Juch Lee. Delay optimization of digital CMOS VLSI circuits by transistor reordering |
| 1193 | -- | 1207 | Abhijit Chatterjee, Charles F. Machala III, Ping Yang. A submicron DC MOSFET model for simulation of analog circuits |
| 1208 | -- | 1222 | Stefan Halama, Christoph Pichler, Gerhard Rieger, Gerhard Schrom, Thomas Simlinger, Siegfried Selberherr. VISTA-user interface, task level, and tool integration |
| 1223 | -- | 1230 | Mark E. Law. Grid adaption near moving boundaries in two dimensions for IC process simulation |
| 1231 | -- | 1240 | Alfred Kwok Kit Wong, Roberto Guerrieri, Andrew R. Neureuther. Massively parallel electromagnetic simulation for photolithographic applications |
| 1241 | -- | 1256 | Wolfgang Meyer, Raul Camposano. Active timing multilevel fault-simulation with switch-level accuracy |
| 1257 | -- | 1267 | Jay B. Brockman, Stephen W. Director. The schema-based approach to workflow management |
| 1268 | -- | 1276 | Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal. A partition and resynthesis approach to testable design of large circuits |
| 1277 | -- | 1290 | Kei-Yong Khoo, Jason Cong. An efficient multilayer MCM router based on four-via routing |
| 1291 | -- | 1298 | Chin-Long Wey, Shoba Krishnan, Sondes Sahli. Test generation and concurrent error detection in current-mode A/D converters |
| 1299 | -- | 1305 | Miquel Roca, Antonio Rubio. Current testability analysis of feedback bridging faults in CMOS circuits |
| 1305 | -- | 1308 | Ching-Wei Yeh. On the acceleration of flow-oriented circuit clustering |