Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

Volume 30, Issue 7

945 -- 959Jude A. Rivers, Meeta Sharma Gupta, Jeonghee Shin, Prabhakar Kudva, Pradip Bose. Error Tolerance in Server Class Processors
960 -- 971Angelo Brambilla, Giambattista Gruosso, Giancarlo Storti Gajani. A Probe-Based Harmonic Balance Method to Simulate Coupled Oscillators
972 -- 985Onder Suvak, Alper Demir. On Phase Models for Oscillators
986 -- 999Yang Zhao, Tao Xu, Krishnendu Chakrabarty. Broadcast Electrode-Addressing and Scheduling Methods for Pin-Constrained Digital Microfluidic Biochips
1000 -- 1010Zigang Xiao, Evangeline F. Y. Young. Placement and Routing for Cross-Referencing Digital Microfluidic Biochips
1011 -- 1019Nikolay Rubanov. A General Framework to Perform the MAX/MIN Operations in Parameterized Statistical Timing Analysis Using Information Theoretic Concepts
1020 -- 1033Jackey Z. Yan, Chris C. N. Chu, Wai-Kei Mak. SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement
1034 -- 1044Jai-Ming Lin, Zhi-Xiong Hung. UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning Considering Pre-Placed Modules
1045 -- 1057Sheng Chou, Cheng-Shen Han, Po-Kai Huang, Ko-Fan Tien, Tsung-Yi Ho. An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis
1058 -- 1071Yen-Tzu Lin, R. D. (Shawn) Blanton. METER: Measuring Test Effectiveness Regionally
1072 -- 1085Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer. BIST-Based Fault Diagnosis for Read-Only Memories