External Links

    Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

    Volume 30, Issue 9

    1265 -- 1278Adam B. Kinsman, Nicola Nicolici. Automated Range and Precision Bit-Width Allocation for Iterative Computations
    1279 -- 1292Weikang Qian, Marc D. Riedel, Hongchao Zhou, Jehoshua Bruck. Transforming Probabilities With Combinational Logic
    1293 -- 1306Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang. Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling
    1307 -- 1320Chenjie Gu. QLMOR: A Projection-Based Nonlinear Model Order Reduction Approach Using Quadratic-Linear Representation of Nonlinear Systems
    1321 -- 1334Cheng Zhuo, Kaviraj Chopra, Dennis Sylvester, David Blaauw. Process Variation and Temperature-Aware Full Chip Oxide Breakdown Reliability Analysis
    1335 -- 1348Yen-Hung Lin, Shu-Hsin Chang, Yih-Lang Li. Critical-Trunk-Based Obstacle-Avoiding Rectilinear Steiner Tree Routings and Buffer Insertion for Delay and Slack Optimization
    1349 -- 1358Jeremy R. Tolbert, Xin Zhao, Sung Kyu Lim, Saibal Mukhopadhyay. Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems
    1359 -- 1372Raid Zuhair Ayoub, Krishnam Raju Indukuri, Tajana Simunic Rosing. Temperature Aware Dynamic Workload Scheduling in Multisocket CPU Servers
    1373 -- 1386Jason Thong, Nicola Nicolici. An Optimal and Practical Approach to Single Constant Multiplication
    1387 -- 1399Daniel Gebhardt, JunBok You, Kenneth S. Stevens. Design of an Energy-Efficient Asynchronous NoC and Its Optimization Tools for Heterogeneous SoCs
    1400 -- 1410Ahcène Bounceur, Salvador Mir, Haralampos-G. D. Stratigopoulos. Estimation of Analog Parametric Test Metrics Using Copulas
    1411 -- 1415Stephan Eggersglüß, Rolf Drechsler. Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application
    1416 -- 1420Irith Pomeranz. Scan Shift Power of Functional Broadside Tests
    1421 -- 1425Erdem Serkan Erdogan, Sule Ozev. A Multi-Site Test Solution for Quadrature Modulation RF Transceivers

    Volume 30, Issue 8

    1089 -- 1102Husni M. Habal, Helmut Graeb. Constraint-Based Layout-Driven Sizing of Analog Circuits
    1103 -- 1113Jie Zhang, Nishant Patil, Arash Hazeghi, H.-S. Philip Wong, Subhasish Mitra. Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations
    1114 -- 1127Seungwhun Paik, Seonggwan Lee, Youngsoo Shin. Retiming Pulsed-Latch Circuits With Regulating Pulse Width
    1128 -- 1140Wei Hu, Jason Oberg, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Dejun Mu, Ryan Kastner. Theoretical Fundamentals of Gate Level Information Flow Tracking
    1141 -- 1151Jorge Fernandez Villena, L. Miguel Silveira. Multi-Dimensional Automatic Sampling Schemes for Multi-Point Modeling Methodologies
    1152 -- 1162Qiang Ma 0002, Zaichen Qian, Evangeline F. Y. Young, Hai Zhou. MSV-Driven Floorplanning
    1163 -- 1172Se Hun Kim, Saibal Mukhopadhyay, Wayne Wolf. Modeling and Analysis of Image Dependence and Its Implications for Energy Savings in Error Tolerant Image Processing
    1173 -- 1183Ali Irturk, Janarbek Matai, Jason Oberg, Jeffrey Su, Ryan Kastner. Simulate and Eliminate: A Top-to-Bottom Design Methodology for Automatic Generation of Application Specific Architectures
    1184 -- 1196Jer Min Jou, Yun-Lung Lee, Sih-Sian Wu. Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware Synthesis
    1197 -- 1210Paul Bogdan, Radu Marculescu. Hitting Time Analysis for Fault-Tolerant Communication at Nanoscale in Future Multiprocessor Platforms
    1211 -- 1224Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto. A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design
    1225 -- 1238Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, P. Szczerbicki, Jerzy Tyszer. Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression
    1239 -- 1252Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler. Effective Robustness Analysis Using Bounded Model Checking Techniques
    1253 -- 1257Irith Pomeranz. Generation of Multi-Cycle Broadside Tests
    1258 -- 1262Ahmed Shebaita, Debasish Das, Dusan Petranovic, Yehea I. Ismail. A Novel Moment Based Framework for Accurate and Efficient Static Timing Analysis

    Volume 30, Issue 7

    945 -- 959Jude A. Rivers, Meeta Sharma Gupta, Jeonghee Shin, Prabhakar Kudva, Pradip Bose. Error Tolerance in Server Class Processors
    960 -- 971Angelo Brambilla, Giambattista Gruosso, Giancarlo Storti Gajani. A Probe-Based Harmonic Balance Method to Simulate Coupled Oscillators
    972 -- 985Onder Suvak, Alper Demir. On Phase Models for Oscillators
    986 -- 999Yang Zhao, Tao Xu, Krishnendu Chakrabarty. Broadcast Electrode-Addressing and Scheduling Methods for Pin-Constrained Digital Microfluidic Biochips
    1000 -- 1010Zigang Xiao, Evangeline F. Y. Young. Placement and Routing for Cross-Referencing Digital Microfluidic Biochips
    1011 -- 1019Nikolay Rubanov. A General Framework to Perform the MAX/MIN Operations in Parameterized Statistical Timing Analysis Using Information Theoretic Concepts
    1020 -- 1033Jackey Z. Yan, Chris C. N. Chu, Wai-Kei Mak. SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement
    1034 -- 1044Jai-Ming Lin, Zhi-Xiong Hung. UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning Considering Pre-Placed Modules
    1045 -- 1057Sheng Chou, Cheng-Shen Han, Po-Kai Huang, Ko-Fan Tien, Tsung-Yi Ho. An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis
    1058 -- 1071Yen-Tzu Lin, R. D. (Shawn) Blanton. METER: Measuring Test Effectiveness Regionally
    1072 -- 1085Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer. BIST-Based Fault Diagnosis for Read-Only Memories

    Volume 30, Issue 6

    793 -- 805Bo Liu, Francisco V. Fernández, Georges G. E. Gielen. Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware Circuit Sizing Based on Computational Intelligence Techniques
    806 -- 816Dmitri Maslov, Mehdi Saeedi. Reversible Circuit Optimization Via Leaving the Boolean Domain
    817 -- 828Cliff Chiung-Yu Lin, Yao-Wen Chang. Cross-Contamination Aware Design Methodology for Pin-Constrained Digital Microfluidic Biochips
    829 -- 840Shahin Golshan, Hessam Kooti, Elaheh Bozorgzadeh. SEU-Aware High-Level Data Path Synthesis and Layout Generation on SRAM-Based FPGAs
    841 -- 851Antonio J. García-Loureiro, Natalia Seoane, Manuel Aldegunde, R. Valin, Asen Asenov, A. Martinez, Karol Kalna. Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors
    852 -- 865Vineeth Veetil, Kaviraj Chopra, David Blaauw, Dennis Sylvester. Fast Statistical Static Timing Analysis Using Smart Monte Carlo Techniques
    866 -- 876Quan Chen, Wim Schoenmaker, Peter Meuris, Ngai Wong. An Effective Formulation of Coupled Electromagnetic-TCAD Simulation for Extremely High Frequency Onward
    877 -- 890Anand Rajaram, David Z. Pan. Robust Chip-Level Clock Tree Synthesis
    891 -- 904Nigel Drego, Anantha P. Chandrakasan, Duane S. Boning, Devavrat Shah. Reduction of Variation-Induced Energy Overhead in Multi-Core Processors
    905 -- 918Kyungsu Kang, Jungsoo Kim, Sungjoo Yoo, Chong-Min Kyung. Runtime Power Management of 3-D Multi-Core Architectures Under Peak Power and Temperature Constraints
    919 -- 929Mincent Lee, Li-Ming Denq, Cheng-Wen Wu. A Memory Built-In Self-Repair Scheme Based on Configurable Spares
    930 -- 934Tong-Yu Hsieh, Kuen-Jong Lee, M. A. Breuer. An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement
    934 -- 939Dani Tannir, Roni Khazaka. Adjoint Sensitivity Analysis of Nonlinear Distortion in Radio Frequency Circuits
    939 -- 944Jason Cong, Hui Huang, Wei Jiang. Pattern-Mining for Behavioral Synthesis

    Volume 30, Issue 5

    637 -- 650Ganghee Lee, Kiyoung Choi, Nikil D. Dutt. Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures
    651 -- 664Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton. Automating Logic Transformations With Approximate SPFDs
    665 -- 677Tejaswi Gowda, Sarma B. K. Vrudhula, N. Kulkarni, Krzysztof S. Berezowski. Identification of Threshold Functions and Synthesis of Threshold Networks
    678 -- 690Aijiao Cui, Chip-Hong Chang, Sofiène Tahar, Amr T. Abdel-Hamid. A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design
    691 -- 703Nahi H. Abdul Ghani, Farid N. Najm. Fast Vectorless Power Grid Verification Under an RLC Model
    704 -- 717Evanthia Papadopoulou. Net-Aware Critical Area Extraction for Opens in VLSI Circuits Via Higher-Order Voronoi Diagrams
    718 -- 731Tao Huang, Liang Li, Evangeline F. Y. Young. On the Construction of Optimal Obstacle-Avoiding Rectilinear Steiner Minimum Trees
    732 -- 745Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim. Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
    746 -- 759Huan Ren, Shantanu Dutt. Effective Power Optimization Under Timing and Voltage-Island Constraints Via Simultaneous V::dd::, V::th:: Assignments, Gate Sizing, and Placement
    760 -- 773Evelyn Mintarno, Joëlle Skaf, Rui Zheng, Jyothi Velamala, Yu Cao, Stephen P. Boyd, Robert W. Dutton, Subhasish Mitra. Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging
    774 -- 786Maurizio Palesi, Giuseppe Ascia, Fabrizio Fazzino, Vincenzo Catania. Data Encoding Schemes in Networks on Chip
    787 -- 791Xrysovalantis Kavousianos, Krishnendu Chakrabarty. Generation of Compact Stuck-At Test Sets Targeting Unmodeled Defects

    Volume 30, Issue 4

    473 -- 491Jason Cong, Bin Liu 0006, Stephen Neuendorffer, Juanjo Noguera, Kees A. Vissers, Zhiru Zhang. High-Level Synthesis for FPGAs: From Prototyping to Deployment
    492 -- 493Luca Benini, Luca P. Carloni. Guest Editorial: Special Section on the ACM/IEEE Symposium on Networks-on-Chip 2010
    494 -- 507Michael N. Horak, Steven M. Nowick, Matthew Carlberg, Uzi Vishkin. A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
    508 -- 519Paul Bogdan, Radu Marculescu. Non-Stationary Traffic Analysis and Its Implications on Multicore Platform Design
    520 -- 533Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano. Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs
    534 -- 547Samuel Rodrigo, José Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesus Camacho, Federico Silla, José Duato. Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems
    548 -- 561Rohit Sunkam Ramanujam, Vassos Soteriou, Bill Lin, Li-Shiuan Peh. Extending the Effective Throughput of NoCs With Distributed Shared-Buffer Routers
    562 -- 573Zhuo Feng, Xueqian Zhao, Zhiyu Zeng. Robust Parallel Preconditioned Power Grid Simulation on GPU With Adaptive Runtime Performance Modeling and Optimization
    574 -- 583Xiao-Chun Li, Jun-Fa Mao, Madhavan Swaminathan. Transient Analysis of CMOS-Gate-Driven RLGC Interconnects Based on FDTD
    584 -- 592Jingtong Hu, Wei-Che Tseng, Chun Jason Xue, Qingfeng Zhuge, Yingchao Zhao, Edwin Hsing-Mean Sha. Write Activity Minimization for Nonvolatile Main Memory Via Scheduling and Recomputation
    593 -- 606Ming-Chao Chiang, Tse-Chen Yeh, Guo-Fu Tseng. A QEMU and SystemC-Based Cycle-Accurate ISS for Performance Estimation on SoC Development
    607 -- 616Jongeun Lee, Aviral Shrivastava. Static Analysis of Register File Vulnerability
    617 -- 630Scott Little, David Walter, Chris J. Myers, Robert Thacker, Satish Batchu, Tomohiro Yoneda. Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets
    631 -- 635Santino Mele, Michele Favalli. A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits

    Volume 30, Issue 3

    325 -- 336Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang. Thermal-Driven Analog Placement Considering Device Matching
    337 -- 349Masoud Rostami, Kartik Mohanram. Dual-V::th:: Independent-Gate FinFETs for Low Power Logic Circuits
    350 -- 363Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, Jose Manuel Mendias, Román Hermida. A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis
    364 -- 373S. Roy, Anestis Dounavis. Transient Simulation of Distributed Networks Using Delay Extraction Based Numerical Convolution
    374 -- 387Pekka Miettinen, Mikko Honkala, Janne Roos, Martti Valtonen. PartMOR: Partitioning-Based Realizable Model-Order Reduction Method for RLC Circuits
    388 -- 401Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He. Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability
    402 -- 415Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng. Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill
    416 -- 426Yifang Liu, Rupesh S. Shelar, Jiang Hu. Simultaneous Technology Mapping and Placement for Delay Minimization
    427 -- 440Ying-Cherng Lan, Yueh-Chi Lin, Shih-Hsin Lo, Yu Hen Hu, Sao-Jie Chen. A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel
    441 -- 454Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu. Automatic Pipelining From Transactional Datapath Specifications
    455 -- 463Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu. Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains
    464 -- 467C. C. Chen, C.-W. Kuo, Y. J. Yang. Generating Passive Compact Models for Piezoelectric Devices
    468 -- 472Young-Pyo Joo, Sungchan Kim, Soonhoi Ha. Fast Communication Architecture Exploration of Processor Pool-Based MPSoC via Static Performance Analysis

    Volume 30, Issue 2

    165 -- 166Prashant Saxena, Yao-Wen Chang. Guest Editorial
    167 -- 179Renshen Wang, Yulei Zhang, Nan-Chi Chou, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham. Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications
    180 -- 193Michael Eick, Martin Strasser, Kun Lu, Ulf Schlichtmann, Helmut E. Graeb. Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits
    194 -- 204Gaurav Ajwani, Chris Chu, Wai-Kei Mak. FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction
    205 -- 214Lijuan Luo, Tan Yan, Qiang Ma 0002, Martin D. F. Wong, Toshiyuki Shibuya. A New Strategy for Simultaneous Escape Based on Boundary Routing
    215 -- 228Tsung-Wei Huang, Tsung-Yi Ho. A Two-Stage Integer Linear Programming-Based Droplet Routing Algorithm for Pin-Constrained Digital Microfluidic Biochips
    229 -- 241Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly. On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
    242 -- 255M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli. An Efficient Gate Library for Ambipolar CNTFET Logic
    256 -- 269Vittorio Rizzoli, Diego Masotti, Franco Mastri, E. Montanari. System-Oriented Harmonic-Balance Algorithms for Circuit-Level Simulation
    270 -- 283Min Gong, Hai Zhou, Li Li, Jun Tao, Xuan Zeng. Binning Optimization for Transparently-Latched Circuits
    284 -- 294Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif. Simultaneous Layout Migration and Decomposition for Double Patterning Technology
    295 -- 307Feng Wang 0004, Yibo Chen, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan. Variation-Aware Task and Communication Mapping for MPSoC Architecture
    308 -- 313Tracey Y. Zhou, Hang Liu, Dian Zhou, Tuna B. Tarim. A Fast Analog Circuit Analysis Algorithm for Design Modification and Verification
    313 -- 317Guo Yu, Peng Li. Hierarchical Analog/Mixed-Signal Circuit Optimization Under Process Variations and Tuning
    317 -- 322Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan. Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies

    Volume 30, Issue 12

    1773 -- 1785Sheng Yang, S. Saqib Khursheed, Bashir M. Al-Hashimi, David Flynn, Sachin Idgunji. Reliable State Retention-Based Embedded Processors Through Monitoring and Recovery
    1786 -- 1799Tsung-Wei Huang, Shih-Yuan Yeh, Tsung-Yi Ho. A Network-Flow Based Pin-Count Aware Routing Algorithm for Broadcast-Addressing EWOD Chips
    1800 -- 1813Kyosun Kim, Sangho Shin, Sung-Mo Kang. Field Programmable Stateful Logic Array
    1814 -- 1827Wangyang Zhang, Xin Li, Frank Liu, Emrah Acar, Rob A. Rutenbar, Ronald D. Blanton. Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits
    1828 -- 1841Roxana Ionutiu, Joost Rommes, Wil H. A. Schilders. SparseRC: Sparsity Preserving Model Reduction for RC Circuits With Many Terminals
    1842 -- 1855Muhammet Mustafa Ozdal, Renato Fernandes Hentschke. An Algorithmic Study of Exact Route Matching for Integrated Circuits
    1856 -- 1869Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang. Pulsed-Latch Aware Placement for Timing-Integrity Optimization
    1870 -- 1882Mark Po-Hung Lin, Chih-Cheng Hsu, Yao-Tsung Chang. Post-Placement Power Optimization With Multi-Bit Flip-Flops
    1883 -- 1896Mohamed M. Sabry, Ayse Kivilcim Coskun, David Atienza, Tajana Simunic Rosing, Thomas Brunschwiler. Energy-Efficient Multiobjective Thermal Control for Liquid-Cooled 3-D Stacked Architectures
    1897 -- 1910Yu-Hsiang Kao, Ming Yang, N. Sertac Artan, H. Jonathan Chao. CNoC: High-Radix Clos Network-on-Chip
    1911 -- 1922Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman. Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out
    1923 -- 1934Junxia Ma, Mohammad Tehranipoor. Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects

    Volume 30, Issue 11

    1585 -- 1598Younghyun Kim, Sangyoung Park, Youngjin Cho, Naehyuck Chang. System-Level Online Power Estimation Using an On-Chip Bus Performance Monitoring Unit
    1599 -- 1609Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Jonghee W. Yoon, Doosan Cho, Yunheung Paek. High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures
    1610 -- 1620Xueqian Zhao, Yonghe Guo, Xiaodao Chen, Zhuo Feng, Shiyan Hu. Hierarchical Cross-Entropy Optimization for Fast On-Chip Decap Budgeting
    1621 -- 1634Duo Ding, J. Andres Torres, David Z. Pan. High Performance Lithography Hotspot Detection With Successively Refined Pattern Identifications and Machine Learning
    1635 -- 1648Young-Joon Lee, Sung Kyu Lim. Co-Optimization and Analysis of Signal, Power, and Thermal Interconnects in 3-D ICs
    1649 -- 1662Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang. Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs
    1663 -- 1676Tushar N. K. Jain, Mukund Ramakrishna, Paul V. Gratz, Alexander Sprintson, Gwan Choi. Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm
    1677 -- 1690Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha. Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors
    1691 -- 1704David Boland, George A. Constantinides. Bounding Variable Values and Round-Off Effects Using Handelman Representations
    1705 -- 1718Brandon Noia, Krishnendu Chakrabarty, Sandeep Kumar Goel, Erik Jan Marinissen, Jouke Verbree. Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs
    1719 -- 1730Shida Zhong, S. Saqib Khursheed, Bashir M. Al-Hashimi. A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects
    1731 -- 1743Chih-Sheng Hou, Jin-Fu Li, Tsu-Wei Tseng. Memory Built-in Self-Repair Planning Framework for RAMs in SoCs
    1744 -- 1757Ozgur Sinanoglu, Sobeeh Almukhaizim. Unified 2-D X-Alignment for Improving the Observability of Response Compactors
    1758 -- 1762Eric A. Foreman, Peter A. Habitz, Ming-C. Cheng, Christino Tamon. Inclusion of Chemical-Mechanical Polishing Variation in Statistical Static Timing Analysis
    1762 -- 1767Zhen Chen, Krishnendu Chakrabarty, Dong Xiang. MVP: Minimum-Violations Partitioning for Reducing Capture Power in At-Speed Delay-Fault Testing
    1767 -- 1772Kuan-Yu Liao, Chia-Yuan Chang, James Chien-Mo Li. A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives

    Volume 30, Issue 10

    1429 -- 1445Vijay Janapa Reddi, David Brooks. Resilient Architectures via Collaborative Design: Maximizing Commodity Processor Performance in the Presence of Variations
    1446 -- 1457Subhankar Mukherjee, Pallab Dasgupta, Siddhartha Mukhopadhyay. Auxiliary Specifications for Context-Sensitive Monitoring of AMS Assertions
    1458 -- 1468Bo Liu, Dixian Zhao, Patrick Reynaert, Georges G. E. Gielen. Synthesis of Integrated Passive Components for High-Frequency RF ICs Based on Evolutionary Computation and Machine Learning Techniques
    1469 -- 1482Xuanxing Xiong, Jia Wang. Dual Algorithms for Vectorless Power Grid Verification Under Linear Current Constraints
    1483 -- 1492Harish S. Bhat, Braxton Osting. 2-D Inductor-Capacitor Lattice Synthesis
    1493 -- 1506Mohammad Ghasemazar, Massoud Pedram. Optimizing the Power-Delay Product of a Linear Pipeline by Opportunistic Time Borrowing
    1507 -- 1520Johnnie Chan, Gilbert Hendry, Keren Bergman, Luca P. Carloni. Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks
    1521 -- 1533Wooyoung Jang, David Z. Pan. Application-Aware NoC Design for Efficient SDRAM Access
    1534 -- 1544Kuen-Jong Lee, Wei-Cheng Lien, Tong-Yu Hsieh. Test Response Compaction via Output Bit Selection
    1545 -- 1555Min Li, Michael S. Hsiao. 3-D Parallel Fault Simulation With GPGPU
    1556 -- 1563ShengYu Shen, Ying Qin, Liquan Xiao, Kefei Wang, Jianmin Zhang, Sikun Li. A Halting Algorithm to Determine the Existence of the Decoder
    1564 -- 1568Lin Yuan, Sean Leventhal, Junjun Gu, Gang Qu. TALk: A Temperature-Aware Leakage Minimization Technique for Real-Time Systems
    1569 -- 1573Tongquan Wei, Xiaodao Chen, Shiyan Hu. Reliability-Driven Energy-Efficient Task Scheduling for Multiprocessor Real-Time Systems
    1574 -- 1578Paolo Maffezzoni, Dario D'Amore. Analysis of Phase Diffusion Process in Oscillators Due to White and Colored-Noise Sources
    1579 -- 1583Irith Pomeranz. Subsets of Primary Input Vectors in Sequential Test Generation for Single Stuck-at Faults

    Volume 30, Issue 1

    1 -- 0Sachin S. Sapatnekar. Editorial
    8 -- 17Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay. Floorplanning for Partially Reconfigurable FPGAs
    18 -- 30Andrew C. Ling, Stephen Dean Brown, Sean Safarpour, Jianwen Zhu. Toward Automated ECOs in FPGAs
    31 -- 44Osnat Keren, Ilya Levin, Radomir S. Stankovic. Determining the Number of Paths in Decision Diagrams by Using Autocorrelation Coefficients
    45 -- 58Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif. Hierarchical Multialgorithm Parallel Circuit Simulation
    59 -- 71Lin Xie, Azadeh Davoodi. Bound-Based Statistically-Critical Path Extraction Under Process Variations
    72 -- 84Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth. GRIP: Global Routing via Integer Programming
    85 -- 95Qiang Ma 0002, Linfu Xiao, Yiu-Cheong Tam, Evangeline F. Y. Young. Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints
    96 -- 109Hochang Jang, Deokjin Joo, Taewhan Kim. Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization
    110 -- 123Jungsoo Kim, Sungjoo Yoo, Chong-Min Kyung. Program Phase-Aware Dynamic Voltage Scaling Under Variable Computational Workload and Memory Stall Environment
    124 -- 134Igor Loi, Federico Angiolini, Shinobu Fujita, Subhasish Mitra, Luca Benini. Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip
    135 -- 147Dong Xiang, Ye Zhang. Cost-Effective Power-Aware Core Testing in NoCs Based on a New Unicast-Based Multicast Scheme
    148 -- 158Sounil Biswas, Ronald D. Blanton. Reducing Test Execution Cost of Integrated, Heterogeneous Systems Using Continuous Test Data
    159 -- 163Javid Jaffari, Mohab Anis. On Efficient LHS-Based Yield Analysis of Analog Circuits
    runs on