| 165 | -- | 166 | Prashant Saxena, Yao-Wen Chang. Guest Editorial |
| 167 | -- | 179 | Renshen Wang, Yulei Zhang, Nan-Chi Chou, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham. Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications |
| 180 | -- | 193 | Michael Eick, Martin Strasser, Kun Lu, Ulf Schlichtmann, Helmut E. Graeb. Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits |
| 194 | -- | 204 | Gaurav Ajwani, Chris Chu, Wai-Kei Mak. FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction |
| 205 | -- | 214 | Lijuan Luo, Tan Yan, Qiang Ma 0002, Martin D. F. Wong, Toshiyuki Shibuya. A New Strategy for Simultaneous Escape Based on Boundary Routing |
| 215 | -- | 228 | Tsung-Wei Huang, Tsung-Yi Ho. A Two-Stage Integer Linear Programming-Based Droplet Routing Algorithm for Pin-Constrained Digital Microfluidic Biochips |
| 229 | -- | 241 | Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly. On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits |
| 242 | -- | 255 | M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli. An Efficient Gate Library for Ambipolar CNTFET Logic |
| 256 | -- | 269 | Vittorio Rizzoli, Diego Masotti, Franco Mastri, E. Montanari. System-Oriented Harmonic-Balance Algorithms for Circuit-Level Simulation |
| 270 | -- | 283 | Min Gong, Hai Zhou, Li Li, Jun Tao, Xuan Zeng. Binning Optimization for Transparently-Latched Circuits |
| 284 | -- | 294 | Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif. Simultaneous Layout Migration and Decomposition for Double Patterning Technology |
| 295 | -- | 307 | Feng Wang 0004, Yibo Chen, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan. Variation-Aware Task and Communication Mapping for MPSoC Architecture |
| 308 | -- | 313 | Tracey Y. Zhou, Hang Liu, Dian Zhou, Tuna B. Tarim. A Fast Analog Circuit Analysis Algorithm for Design Modification and Verification |
| 313 | -- | 317 | Guo Yu, Peng Li. Hierarchical Analog/Mixed-Signal Circuit Optimization Under Process Variations and Tuning |
| 317 | -- | 322 | Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan. Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies |