| 325 | -- | 336 | Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang. Thermal-Driven Analog Placement Considering Device Matching |
| 337 | -- | 349 | Masoud Rostami, Kartik Mohanram. Dual-V::th:: Independent-Gate FinFETs for Low Power Logic Circuits |
| 350 | -- | 363 | Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, Jose Manuel Mendias, Román Hermida. A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis |
| 364 | -- | 373 | S. Roy, Anestis Dounavis. Transient Simulation of Distributed Networks Using Delay Extraction Based Numerical Convolution |
| 374 | -- | 387 | Pekka Miettinen, Mikko Honkala, Janne Roos, Martti Valtonen. PartMOR: Partitioning-Based Realizable Model-Order Reduction Method for RLC Circuits |
| 388 | -- | 401 | Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He. Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability |
| 402 | -- | 415 | Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng. Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill |
| 416 | -- | 426 | Yifang Liu, Rupesh S. Shelar, Jiang Hu. Simultaneous Technology Mapping and Placement for Delay Minimization |
| 427 | -- | 440 | Ying-Cherng Lan, Yueh-Chi Lin, Shih-Hsin Lo, Yu Hen Hu, Sao-Jie Chen. A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel |
| 441 | -- | 454 | Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu. Automatic Pipelining From Transactional Datapath Specifications |
| 455 | -- | 463 | Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu. Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains |
| 464 | -- | 467 | C. C. Chen, C.-W. Kuo, Y. J. Yang. Generating Passive Compact Models for Piezoelectric Devices |
| 468 | -- | 472 | Young-Pyo Joo, Sungchan Kim, Soonhoi Ha. Fast Communication Architecture Exploration of Processor Pool-Based MPSoC via Static Performance Analysis |