| 1 | -- | 0 | Sachin S. Sapatnekar. Editorial |
| 8 | -- | 17 | Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay. Floorplanning for Partially Reconfigurable FPGAs |
| 18 | -- | 30 | Andrew C. Ling, Stephen Dean Brown, Sean Safarpour, Jianwen Zhu. Toward Automated ECOs in FPGAs |
| 31 | -- | 44 | Osnat Keren, Ilya Levin, Radomir S. Stankovic. Determining the Number of Paths in Decision Diagrams by Using Autocorrelation Coefficients |
| 45 | -- | 58 | Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif. Hierarchical Multialgorithm Parallel Circuit Simulation |
| 59 | -- | 71 | Lin Xie, Azadeh Davoodi. Bound-Based Statistically-Critical Path Extraction Under Process Variations |
| 72 | -- | 84 | Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth. GRIP: Global Routing via Integer Programming |
| 85 | -- | 95 | Qiang Ma 0002, Linfu Xiao, Yiu-Cheong Tam, Evangeline F. Y. Young. Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints |
| 96 | -- | 109 | Hochang Jang, Deokjin Joo, Taewhan Kim. Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization |
| 110 | -- | 123 | Jungsoo Kim, Sungjoo Yoo, Chong-Min Kyung. Program Phase-Aware Dynamic Voltage Scaling Under Variable Computational Workload and Memory Stall Environment |
| 124 | -- | 134 | Igor Loi, Federico Angiolini, Shinobu Fujita, Subhasish Mitra, Luca Benini. Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip |
| 135 | -- | 147 | Dong Xiang, Ye Zhang. Cost-Effective Power-Aware Core Testing in NoCs Based on a New Unicast-Based Multicast Scheme |
| 148 | -- | 158 | Sounil Biswas, Ronald D. Blanton. Reducing Test Execution Cost of Integrated, Heterogeneous Systems Using Continuous Test Data |
| 159 | -- | 163 | Javid Jaffari, Mohab Anis. On Efficient LHS-Based Yield Analysis of Analog Circuits |