| 1 | -- | 0 | Sachin S. Sapatnekar. Editorial |
| 7 | -- | 8 | Diana Marculescu, Peng Li. Guest Editorial Special Section on PAR-CAD: Parallel CAD Algorithms and CAD for Parallel Architectures/Systems |
| 9 | -- | 22 | Nachiket Kapre, André DeHon. ${\rm SPICE}^2$: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA |
| 23 | -- | 36 | Arvind Sridhar, Alessandro Vincenzi, Martino Ruggiero, David Atienza. Neural Network-Based Thermal Simulation of Integrated Circuits on GPUs |
| 37 | -- | 49 | Jorge Fernandez Villena, Luis Miguel Silveira. Exploiting Parallelism for Improved Automation of Multidimensional Model Order Reduction |
| 50 | -- | 60 | Myung-Chul Kim, DongJin Lee, Igor L. Markov. SimPL: An Effective Placement Algorithm |
| 61 | -- | 74 | Marcel Gort, Jason Helge Anderson. Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010 |
| 75 | -- | 88 | Melinda Y. Agyekum, Steven M. Nowick. Error-Correcting Unordered Codes and Hardware Support for Robust Asynchronous Global Communication |
| 89 | -- | 100 | Ibrahim N. Hajj. Extended Nodal Analysis |
| 101 | -- | 108 | Yinghong Zhou, Emad Gad, Michel S. Nakhla, Ramachandra Achar. Structural Characterization and Efficient Implementation Techniques for $A$-Stable High-Order Integration Methods |
| 109 | -- | 120 | Yuanzhe Wang, Xiang Hu, Chung-Kuan Cheng, Grantham K. H. Pang, Ngai Wong. A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints |
| 121 | -- | 131 | Dukyoung Yun, Sungchan Kim, Soonhoi Ha. A Parallel Simulation Technique for Multicore Embedded Systems and Its Performance Analysis |
| 132 | -- | 145 | Chengmo Yang, Alex Orailoglu. Tackling Resource Variations Through Adaptive Multicore Execution Frameworks |
| 146 | -- | 159 | Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. Memory-Efficient On-Chip Network With Adaptive Interfaces |
| 160 | -- | 164 | Bing Shi, Yufu Zhang, Ankur Srivastava. Accelerating Gate Sizing Using Graphics Processing Units |