Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

Volume 31, Issue 9

1305 -- 1318Chirag Ravishankar, Jason Helge Anderson, Andrew A. Kennings. FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture
1319 -- 1331Hsiou-Yuan Liu, Yen-Cheng Chou, Chen-Hsuan Lin, Jie-Hong R. Jiang. Automatic Decoder Synthesis: Methods and Case Studies
1332 -- 1345Parijat Mukherjee, G. Peter Fang, Rod Burt, Peng Li. Efficient Identification of Unstable Loops in Large Linear Analog Integrated Circuits
1346 -- 1355Angelo Brambilla, Giambattista Gruosso, Giancarlo Storti Gajani. MTFS: Mixed Time-Frequency Method for the Steady-State Analysis of Almost-Periodic Nonlinear Circuits
1356 -- 1365Qiang Ma 0002, Martin D. F. Wong. NP-Completeness and an Approximation Algorithm for Rectangle Escape Problem With Application to PCB Routing
1366 -- 1378Meng-Kai Hsu, Yao-Wen Chang. Unified Analytical Global Placement for Large-Scale Mixed-Size Circuit Designs
1379 -- 1392Rani S. Ghaida, Puneet Gupta. DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies
1393 -- 1404Xin-Wei Shih, Yao-Wen Chang. Fast Timing-Model Independent Buffered Clock-Tree Synthesis
1405 -- 1416Xiaochun Yu, R. D. (Shawn) Blanton. Diagnosis-Assisted Adaptive Test
1417 -- 1427Joon-Sung Yang, Nur A. Touba. X-Canceling MISR Architectures for Output Response Compaction With Unknown Values
1428 -- 1438Irith Pomeranz. Multicycle Tests With Constant Primary Input Vectors for Increased Fault Coverage
1439 -- 1451Ansuman Banerjee. Verifying Coalitions in 3-Party Systems
1452 -- 1456Jyotirmoy Ghosh, Siddhartha Mukhopadhyay, Amit Patra, Barry Culpepper, Tawen Mei. Estimation of dc Performance of a Lateral Power MOSFET Using Distributed Cell Model
1457 -- 1461Hubert Filiol, Ian O'Connor, Dominique Morche. Analog IC Variability Bound Estimation Using the Cornish-Fisher Expansion

Volume 31, Issue 8

1145 -- 1158Michael Eick, Helmut E. Graeb. MARS: Matching-Driven Analog Sizing
1159 -- 1168Xiaoke Qin, Weixun Wang, Prabhat Mishra. TCEC: Temperature and Energy-Constrained Scheduling in Real-Time Multitasking Systems
1169 -- 1179Byeong Yong Kong, In-Cheol Park. FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis
1180 -- 1193Shih-Hung Weng, Quan Chen, Chung-Kuan Cheng. Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive Control
1194 -- 1207Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim. TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC
1208 -- 1221Jianli Chen, Wenxing Zhu. An Analytical Placer for VLSI Standard Cell Placement
1222 -- 1234Xin Zhao, Jeremy R. Tolbert, Saibal Mukhopadhyay, Sung Kyu Lim. Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits
1235 -- 1248Arseniy Vitkovskiy, Vassos Soteriou, Chrysostomos Nicopoulos. A Dynamically Adjusting Gracefully Degrading Link-Level Fault-Tolerant Mechanism for NoCs
1249 -- 1262Hoang M. Le, Daniel Große, Rolf Drechsler. Automatic TLM Fault Localization for SystemC
1263 -- 1274Xiao Liu, Qiang Xu. On Signal Selection for Visibility Enhancement in Trace-Based Post-Silicon Validation
1275 -- 1287Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham. Testability-Driven Statistical Path Selection
1288 -- 1292ShengYu Shen, Ying Qin, Kefei Wang, Zhengbin Pang, Jianmin Zhang, Sikun Li. Inferring Assertion for Complementary Synthesis
1293 -- 1297Eric A. Foreman, Peter A. Habitz, Ming-C. Cheng, Chandu Visweswariah. A Novel Method for Reducing Metal Variation With Statistical Static Timing Analysis
1297 -- 1302Allon Adir, Amir Nahir, Avi Ziv. Concurrent Generation of Concurrent Programs for Post-Silicon Validation

Volume 31, Issue 7

981 -- 993Bo Liu, Noël Deferm, Dixian Zhao, Patrick Reynaert, Georges G. E. Gielen. An Efficient High-Frequency Linear RF Amplifier Synthesis Method Based on Evolutionary Computation and Machine Learning Techniques
994 -- 1007Xiangyu Dong, Cong Xu, Yuan Xie, Norman P. Jouppi. NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
1008 -- 1018Lin Xie, Azadeh Davoodi. Post-Silicon Failing-Path Isolation Incorporating the Effects of Process Variations
1019 -- 1030Seungwhun Paik, Inhak Han, Sangmin Kim, Youngsoo Shin. Clock Gating Synthesis of Pulsed-Latch Circuits
1031 -- 1040Quan Chen, Shih-Hung Weng, Chung-Kuan Cheng. A Practical Regularization Technique for Modified Nodal Analysis in Large-Scale Time-Domain Circuit Simulation
1041 -- 1049Ming-Chao Lee, Yiyu Shi, Shih-Chieh Chang. Efficient Wakeup Scheduling Considering Both Resource Usage and Timing Budget for Power Gating Designs
1050 -- 1060Chih-Hung Liu, Sy-Yen Kuo, D. T. Lee, Chun-Syun Lin, Jung-Hung Weng, Shih-Yi Yuan. Obstacle-Avoiding Rectilinear Steiner Tree Construction: A Steiner-Point-Based Algorithm
1061 -- 1073Turbo Majumder, Michael Edward Borgens, Partha Pratim Pande, Ananth Kalyanaraman. On-Chip Network-Enabled Multicore Platforms Targeting Maximum Likelihood Phylogeny Reconstruction
1074 -- 1087Hao Shen, Mian Muhammad Hamayun, Frédéric Pétrot. Native Simulation of MPSoC Using Hardware-Assisted Virtualization
1088 -- 1101Vishwanath Natarajan, Hyun Woo Choi, Aritra Banerjee, Shreyas Sen, Abhijit Chatterjee, Ganesh Srinivasan, Friedrich Taenzler, Soumendu Bhattacharya. Low Cost EVM Testing of Wireless RF SoC Front-Ends Using Multitones
1102 -- 1115Mingjing Chen, Alex Orailoglu. On Diagnosis of Timing Failures in Scan Architecture
1116 -- 1128Haralampos-G. D. Stratigopoulos. Test Metrics Model for Analog Test Development
1129 -- 1134Jussi H. Poikonen, Eero Lehtonen, Mika Laiho. On Synthesis of Boolean Expressions for Memristive Devices Using Sequential Implication Logic
1134 -- 1139Yu-Yi Liang, Tien-Yu Kuo, Shao-Huan Wang, Wai-Kei Mak. ALMmap: Technology Mapping for FPGAs With Adaptive Logic Modules
1139 -- 1143Tom Smy, Pavan K. Gunupudi. Robust Simulation of Opto-Electronic Systems by Alternating Complex Envelope Representations

Volume 31, Issue 6

817 -- 830Yang Zhao, Krishnendu Chakrabarty. Cross-Contamination Avoidance for Droplet Routing in Digital Microfluidic Biochips
831 -- 844Xue-Yang Zhu, Twan Basten, Marc Geilen, Sander Stuijk. Efficient Retiming of Multirate DSP Algorithms
845 -- 857Mu-Shun Matt Lee, Wei-Ting Liao, Chien-Nan Jimmy Liu. Levelized High-Level Current Model of Logic Blocks for Dynamic Supply Noise Analysis
858 -- 867Komail M. H. Badami, Shreepad Karmalkar. Quasi-Static Compact Model for Coupling Between Aligned Contacts on Finite Substrates With Insulating or Conducting Backplanes
868 -- 877Haifeng Qian, Phillip J. Restle, Joseph N. Kozhaya, Clifford L. Gunion. Subtractive Router for Tree-Driven-Grid Clocks
878 -- 889Chung-Wei Lin, Po-Wei Lee, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng. An Efficient Pre-Assignment Routing Algorithm for Flip-Chip Designs
890 -- 903Pengju Ren, Mieszko Lis, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Nanning Zheng, Srinivas Devadas. HORNET: A Cycle-Level Multicore Simulator
904 -- 917Jin Cui, Douglas L. Maskell. A Fast High-Level Event-Driven Thermal Estimator for Dynamic Thermal Aware Scheduling
918 -- 929Wing Chiu Tam, R. D. (Shawn) Blanton. SLIDER: Simulation of Layout-Injected Defects for Electrical Responses
930 -- 940Ting-Ju Chen, Jin-Fu Li, Tsu-Wei Tseng. Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs
941 -- 949Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian. A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs
950 -- 957Thomas Rabenalt, Michael Richter, Frank Poehl, Michael Gössel. Highly Efficient Test Response Compaction Using a Hierarchical X-Masking Technique
958 -- 967Afsaneh Nassery, Osman Emir Erol, Sule Ozev, Marian Verhelst. Test Signal Development and Analysis for OFDM Systems RF Front-End Parameter Extraction
968 -- 979Ender Yilmaz, Sule Ozev. Test Application for Analog/RF Circuits With Low Computational Burden

Volume 31, Issue 5

649 -- 661Xin Jin, Satoshi Goto. Hilbert Transform-Based Workload Prediction and Dynamic Frequency Scaling for Power-Efficient Video Encoding
662 -- 675Lu Wan, Deming Chen. Analysis of Digital Circuit Dynamic Behavior With Timed Ternary Decision Diagrams for Better-Than-Worst-Case Design
676 -- 689Samson Melamed, Thorlindur Thorolfsson, T. Robert Harris, Shivam Priyadarshi, Paul D. Franzon, Michael B. Steer, W. Rhett Davis. Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High Definition Power Blurring
690 -- 702Abde Ali Kagalwalla, Puneet Gupta, Christopher J. Progler, Steve McDonald. Design-Aware Mask Inspection
703 -- 716Shao-Yun Fang, Szu-Yu Chen, Yao-Wen Chang. Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology
717 -- 725Hassan Salamy, J. Ramanujam. An Effective Solution to Task Scheduling and Memory Partitioning for Multiprocessor System-on-Chip
726 -- 739Andrew DeOrio, David Fick, Valeria Bertacco, Dennis Sylvester, David Blaauw, Jin Hu, Gregory K. Chen. A Reliable Routing Architecture and Algorithm for NoCs
740 -- 753Giovanni Mariani, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano. OSCAR: An Optimization Methodology Exploiting Spatial Correlation in Multicore Design Spaces
754 -- 764Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer. Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement
765 -- 778Hana Chockler, Daniel Kroening, Mitra Purandare. Computing Mutation Coverage in Interpolation-Based Model Checking
779 -- 789Tobias Welp, Nathan Kitchen, Andreas Kuehlmann. Hardware Acceleration for Constraint Solving for Random Simulation
790 -- 803Lingyi Liu, David Sheridan, William Tuohy, Shobha Vasudevan. A Technique for Test Coverage Closure Using GoldMine
804 -- 808Yao-Lin Jiang, Hai-Bao Chen. Application of General Orthogonal Polynomials to Fast Simulation of Nonlinear Descriptor Systems Through Piecewise-Linear Approximation
809 -- 813Elif Alpaslan, Bram Kruseman, Ananta K. Majhi, Wilmar M. Heuvelman, Jennifer Dworak. NIM-X: A Noise Index Model-Based X-Filling Technique to Overcome the Power Supply Switching Noise Effects on Path Delay Test

Volume 31, Issue 4

453 -- 471Jie Zhang, Albert Lin, Nishant Patil, Hai Wei, Lan Wei, H.-S. Philip Wong, Subhasish Mitra. Carbon Nanotube Robust Digital VLSI
472 -- 484Khaled R. Heloue, Sari Onaissi, Farid N. Najm. Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths
485 -- 496Jaeyong Chung, Jacob A. Abraham. Refactoring of Timing Graphs and Its Use in Capturing Topological Correlation in SSTA
497 -- 508Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham. Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator
509 -- 521Walid Ibrahim, Valeriu Beiu, Azam Beg. GREDA: A Fast and More Accurate Gate Reliability EDA Tool
522 -- 531Tom J. Kazmierski, Leran Wang, Bashir M. Al-Hashimi, Geoff V. Merrett. An Explicit Linearized State-Space Technique for Accelerated Simulation of Electromagnetic Vibration Energy Harvesters
532 -- 545Yuanzhe Wang, Zheng Zhang, Cheng-Kok Koh, Guoyong Shi, Grantham K. H. Pang, Ngai Wong. Passivity Enforcement for Descriptor Systems Via Matrix Pencil Perturbation
546 -- 558Hyungmin Cho, Larkhoon Leem, Subhasish Mitra. ERSA: Error Resilient System Architecture for Probabilistic Applications
559 -- 572Hyunsun Park, Sungjoo Yoo, Sunggu Lee. A Multistep Tag Comparison Method for a Low-Power L2 Cache
573 -- 585Giorgos Passas, Manolis Katevenis, Dionisios N. Pnevmatikatos. Crossbar NoCs Are Scalable Beyond 100 Nodes
586 -- 596Sonali Chouhan, M. Balakrishnan, Ranjan Bose. System-Level Design Space Exploration Methodology for Energy-Efficient Sensor Node Configurations: An Experimental Validation
597 -- 609Hao-Chiao Hong. A Static Linear Behavior Analog Fault Model for Switched-Capacitor Circuits
610 -- 619Dongsoo Lee, Kaushik Roy. Viterbi-Based Efficient Test Data Compression
620 -- 629Shyue-Kung Lu, Zhen-Yu Wang, Yi-Ming Tsai, Jiann-Liang Chen. Efficient Built-In Self-Repair Techniques for Multiple Repairable Embedded RAMs
630 -- 643Hongxia Fang, Krishnendu Chakrabarty, Zhiyuan Wang, Xinli Gu. Reproduction and Detection of Board-Level Functional Failure
644 -- 648Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Cheng-Ho Chang. $2^{n}$ Pattern Run-Length for Test Data Compression

Volume 31, Issue 3

329 -- 342Alireza Ejlali, Bashir M. Al-Hashimi, Petru Eles. Low-Energy Standby-Sparing for Hard Real-Time Systems
343 -- 355Omid Sarbishei, Katarzyna Radecka, Zeljko Zilic. Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems
356 -- 369Mingzhi Gao, Zuochang Ye, Yan Wang, Zhiping Yu. Efficient Full-Chip Statistical Leakage Analysis Based on Fast Matrix Vector Product
370 -- 379Chun-Jen Wei, Howard Chen, Sao-Jie Chen. Design and Implementation of Block-Based Partitioning for Parallel Flip-Chip Power-Grid Analysis
380 -- 390Jongwon Lee, Duo Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Dan Jiao. A Quadratic Eigenvalue Solver of Linear Complexity for 3-D Electromagnetics-Based Analysis of Large-Scale Integrated Circuits
391 -- 403Jun Seomun, Insup Shin, Youngsoo Shin. Synthesis of Active-Mode Power-Gating Circuits
404 -- 417Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori. Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors
418 -- 431Elena Kakoulli, Vassos Soteriou, Theocharis Theocharides. Intelligent Hotspot Prediction for Network-on-Chip-Based Multicore Systems
432 -- 436Paolo Maffezzoni. Stochastic Analysis of Switched-Capacitor Circuits for Sampled Data Converters
437 -- 441Zhuo Li, Ying Zhou, Weiping Shi. $O(mn)$ Time Algorithm for Optimal Buffer Insertion of Nets With $m$ Sinks
442 -- 446Joon-Sung Yang, Nur A. Touba. Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis
447 -- 451Sourasis Das, Ansuman Banerjee, Pallab Dasgupta. Early Analysis of Critical Faults: An Approach to Test Generation From Formal Specifications
452 -- 0Yuanzhe Wang, Xiang Hu, Chung-Kuan Cheng, Grantham K. H. Pang, Ngai Wong. Corrigendum to "A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints"

Volume 31, Issue 2

165 -- 166Jiang Hu, Cheng-Kok Koh. Guest Editorial Special Section on the 2011 International Symposium on Physical Design
167 -- 179Kun Yuan, Bei Yu, David Z. Pan. E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters
180 -- 191Shao-Huan Wang, Yu-Yi Liang, Tien-Yu Kuo, Wai-Kei Mak. ISPD11: Power-Driven Flip-Flop Merging and Relocation
192 -- 204Iris Hui-Ru Jiang, Chih-Long Chang, Yu-Ming Yang. INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving
205 -- 216DongJin Lee, Igor L. Markov. Obstacle-Aware Clock-Tree Shaping During Placement
217 -- 227Jianchao Lu, Xiaomi Mao, Baris Taskin. Integrated Clock Mesh Synthesis With Incremental Register Placement
228 -- 241Johann Knechtel, Igor L. Markov, Jens Lienig. Assembling 2-D Blocks Into 3-D Chips
242 -- 254Yang Zhao, Krishnendu Chakrabarty. Simultaneous Optimization of Droplet Routing and Control-Pin Mapping to Electrodes in Digital Microfluidic Biochips
255 -- 259Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze. Postgrid Clock Routing for High Performance Microprocessor Designs
260 -- 270Yung-Chih Chen, Chun-Yao Wang. Logic Restructuring Using Node Addition and Removal
271 -- 284Hratch Mangassarian, Andreas G. Veneris, Farid N. Najm. Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability
285 -- 293Tan Yan, Martin D. F. Wong. Correctly Model the Diagonal Capacity in Escape Routing
294 -- 307Carles Hernández, Antoni Roca, Federico Silla, Jose Flich, José Duato. On the Impact of Within-Die Process Variation in GALS-Based NoC Performance
308 -- 321Yen-Tzu Lin, Osei Poku, R. D. (Shawn) Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar. Physically-Aware N-Detect Test
322 -- 326Irith Pomeranz. Multipattern Scan-Based Test Sets With Small Numbers of Primary Input Sequences

Volume 31, Issue 12

1789 -- 1802Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang. Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors
1803 -- 1816Giovanni Ansaloni, Kazuyuki Tanimura, Laura Pozzi, Nikil Dutt. Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays
1817 -- 1830Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, José M. Mendías, María C. Molina. Multispeculative Addition Applied to Datapath Synthesis
1831 -- 1844Shupeng Sun, Yamei Feng, Changdao Dong, Xin Li. Efficient SRAM Failure Rate Prediction via Gibbs Sampling
1845 -- 1856Zahra Lak, Nicola Nicolici. On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging
1857 -- 1866Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang. Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification
1867 -- 1880Sudarshan Srinivasan, Kunal P. Ganeshpure, Sandip Kundu. A Wavelet-Based Spatio-Temporal Heat Dissipation Model for Reordering of Program Phases to Produce Temperature Extremes in a Chip
1881 -- 1893Nicolas G. Constantin, Kai H. Kwok, Hongxiao Shao, Cristian Cismaru, Peter J. Zampardi. Formulations and a Computer-Aided Test Method for the Estimation of IMD Levels in an Envelope Feedback RFIC Power Amplifier
1894 -- 1907Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer. EDT Bandwidth Management in SoC Designs
1908 -- 1919Michael A. Kochte, Melanie Elm, Hans-Joachim Wunderlich. Accurate X-Propagation for Test Applications by SAT-Based Reasoning
1920 -- 1924Janakiraman Viraraghavan, Shrinivas J. Pandharpure, Josef Watts. Statistical Compact Model Extraction: A Neural Network Approach
1925 -- 1929Paolo Maffezzoni, Salvatore Levantino. Phase-Noise Analysis and Simulation of LC Oscillator-Based Injection-Locked Frequency Dividers
1930 -- 1934Katherine Shu-Min Li, Yi-Yu Liao. Layout-Aware Multiple Scan Tree Synthesis for 3-D SoCs
1935 -- 1939Jaeyong Chung, Jacob A. Abraham. On Computing Criticality in Refactored Timing Graphs

Volume 31, Issue 11

1629 -- 1641Timothée Levi, Noëlle Lewis, Jean Tomas, Sylvie Renaud. Application of IP-Based Analog Platforms in the Design of Neuromimetic Integrated Circuits
1642 -- 1655Dogan Fennibay, Arda Yurdakul, Alper Sen 0001. A Heterogeneous Simulation and Modeling Framework for Automation Systems
1656 -- 1669Yi-Ling Hsieh, Tsung-Yi Ho, Krishnendu Chakrabarty. A Reagent-Saving Mixing Algorithm for Preparing Multiple-Target Biochemical Samples Using Digital Microfluidics
1670 -- 1683Bing Li, Ning Chen, Ulf Schlichtmann. Statistical Timing Analysis for Latch-Controlled Circuits With Reduced Iterations and Graph Transformations
1684 -- 1697Jongyoon Jung, Taewhan Kim. Variation-Aware False Path Analysis Based on Statistical Dynamic Timing Analysis
1698 -- 1710Chuan Xu, Navin Srivastava, Roberto Suaya, Kaustav Banerjee. Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates
1711 -- 1722Wai-Kei Mak, Yu-Chen Lin, Chris Chu, Ting-Chi Wang. Pad Assignment for Die-Stacking System-in-Package Design
1723 -- 1733Kuan-Hsien Ho, Jie-Hong Roland Jiang, Yao-Wen Chang. TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders
1734 -- 1742Irith Pomeranz. A Metric for Identifying Detectable Path Delay Faults
1743 -- 1753Xiao Liu, Qiang Xu. On X-Variable Filling and Flipping for Capture-Power Reduction in Linear Decompressor-Based Test Compression Environment
1754 -- 1766Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji. Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands
1767 -- 1771Dongkeun Oh, Charlie Chung-Ping Chen, Yu Hen Hu. Efficient Thermal Simulation for 3-D IC With Thermal Through-Silicon Vias
1772 -- 1776Subhankar Mukherjee, Pallab Dasgupta. Assertion Aware Sampling Refinement: A Mixed-Signal Perspective
1776 -- 1781Subhankar Mukherjee, Pallab Dasgupta. Computing Minimal Debugging Windows in Failure Traces of AMS Assertions
1781 -- 1786Rupesh S. Shelar. A Fast and Near-Optimal Clustering Algorithm for Low-Power Clock Tree Synthesis

Volume 31, Issue 10

1465 -- 1484Massoud Pedram. Energy-Efficient Datacenters
1485 -- 1498Ashish Kumar Singh, Kareem Ragab, Mario Lok, Constantine Caramanis, Michael Orshansky. Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics
1499 -- 1507Salvatore Levantino, Paolo Maffezzoni. Computing the Perturbation Projection Vector of Oscillators via Frequency Domain Analysis
1508 -- 1521Rohit Sinha, Hiren D. Patel. synASM: A High-Level Synthesis Framework With Support for Parallel and Timed Constructs
1522 -- 1535Shivam Priyadarshi, Christopher S. Saunders, Nikhil Kriplani, Harun Demircioglu, W. Rhett Davis, Paul D. Franzon, Michael B. Steer. Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning
1536 -- 1545Dongchul Kim, Hyewon Kim, Yungseon Eo. Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Single Interconnect Lines
1546 -- 1557Kai-Ti Hsu, Subarna Sinha, Yu-Chuan Pi, Tsung-Yi Ho. A Hierarchy-Based Distributed Algorithm for Layout Geometry Operations
1558 -- 1571Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu. Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs
1572 -- 1585Jens Gladigau, Christian Haubelt, Jürgen Teich. Model-Based Virtual Prototype Acceleration
1586 -- 1599Hongxia Fang, Krishnendu Chakrabarty, Zhiyuan Wang, Xinli Gu. Diagnosis of Board-Level Functional Failures Under Uncertainty Using Dempster-Shafer Theory
1600 -- 1613Yu-Jen Huang, Jin-Fu Li. Built-In Self-Repair Scheme for the TSVs in 3-D ICs
1614 -- 1625Xiaochun Yu, Ronald D. Blanton. Improving Diagnosis Through Failing Behavior Identification

Volume 31, Issue 1

1 -- 0Sachin S. Sapatnekar. Editorial
7 -- 8Diana Marculescu, Peng Li. Guest Editorial Special Section on PAR-CAD: Parallel CAD Algorithms and CAD for Parallel Architectures/Systems
9 -- 22Nachiket Kapre, André DeHon. ${\rm SPICE}^2$: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA
23 -- 36Arvind Sridhar, Alessandro Vincenzi, Martino Ruggiero, David Atienza. Neural Network-Based Thermal Simulation of Integrated Circuits on GPUs
37 -- 49Jorge Fernandez Villena, Luis Miguel Silveira. Exploiting Parallelism for Improved Automation of Multidimensional Model Order Reduction
50 -- 60Myung-Chul Kim, DongJin Lee, Igor L. Markov. SimPL: An Effective Placement Algorithm
61 -- 74Marcel Gort, Jason Helge Anderson. Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010
75 -- 88Melinda Y. Agyekum, Steven M. Nowick. Error-Correcting Unordered Codes and Hardware Support for Robust Asynchronous Global Communication
89 -- 100Ibrahim N. Hajj. Extended Nodal Analysis
101 -- 108Yinghong Zhou, Emad Gad, Michel S. Nakhla, Ramachandra Achar. Structural Characterization and Efficient Implementation Techniques for $A$-Stable High-Order Integration Methods
109 -- 120Yuanzhe Wang, Xiang Hu, Chung-Kuan Cheng, Grantham K. H. Pang, Ngai Wong. A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints
121 -- 131Dukyoung Yun, Sungchan Kim, Soonhoi Ha. A Parallel Simulation Technique for Multicore Embedded Systems and Its Performance Analysis
132 -- 145Chengmo Yang, Alex Orailoglu. Tackling Resource Variations Through Adaptive Multicore Execution Frameworks
146 -- 159Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. Memory-Efficient On-Chip Network With Adaptive Interfaces
160 -- 164Bing Shi, Yufu Zhang, Ankur Srivastava. Accelerating Gate Sizing Using Graphics Processing Units