| 1145 | -- | 1158 | Michael Eick, Helmut E. Graeb. MARS: Matching-Driven Analog Sizing |
| 1159 | -- | 1168 | Xiaoke Qin, Weixun Wang, Prabhat Mishra. TCEC: Temperature and Energy-Constrained Scheduling in Real-Time Multitasking Systems |
| 1169 | -- | 1179 | Byeong Yong Kong, In-Cheol Park. FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis |
| 1180 | -- | 1193 | Shih-Hung Weng, Quan Chen, Chung-Kuan Cheng. Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive Control |
| 1194 | -- | 1207 | Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim. TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC |
| 1208 | -- | 1221 | Jianli Chen, Wenxing Zhu. An Analytical Placer for VLSI Standard Cell Placement |
| 1222 | -- | 1234 | Xin Zhao, Jeremy R. Tolbert, Saibal Mukhopadhyay, Sung Kyu Lim. Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits |
| 1235 | -- | 1248 | Arseniy Vitkovskiy, Vassos Soteriou, Chrysostomos Nicopoulos. A Dynamically Adjusting Gracefully Degrading Link-Level Fault-Tolerant Mechanism for NoCs |
| 1249 | -- | 1262 | Hoang M. Le, Daniel Große, Rolf Drechsler. Automatic TLM Fault Localization for SystemC |
| 1263 | -- | 1274 | Xiao Liu, Qiang Xu. On Signal Selection for Visibility Enhancement in Trace-Based Post-Silicon Validation |
| 1275 | -- | 1287 | Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham. Testability-Driven Statistical Path Selection |
| 1288 | -- | 1292 | ShengYu Shen, Ying Qin, Kefei Wang, Zhengbin Pang, Jianmin Zhang, Sikun Li. Inferring Assertion for Complementary Synthesis |
| 1293 | -- | 1297 | Eric A. Foreman, Peter A. Habitz, Ming-C. Cheng, Chandu Visweswariah. A Novel Method for Reducing Metal Variation With Statistical Static Timing Analysis |
| 1297 | -- | 1302 | Allon Adir, Amir Nahir, Avi Ziv. Concurrent Generation of Concurrent Programs for Post-Silicon Validation |