| 1305 | -- | 1318 | Chirag Ravishankar, Jason Helge Anderson, Andrew A. Kennings. FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture |
| 1319 | -- | 1331 | Hsiou-Yuan Liu, Yen-Cheng Chou, Chen-Hsuan Lin, Jie-Hong R. Jiang. Automatic Decoder Synthesis: Methods and Case Studies |
| 1332 | -- | 1345 | Parijat Mukherjee, G. Peter Fang, Rod Burt, Peng Li. Efficient Identification of Unstable Loops in Large Linear Analog Integrated Circuits |
| 1346 | -- | 1355 | Angelo Brambilla, Giambattista Gruosso, Giancarlo Storti Gajani. MTFS: Mixed Time-Frequency Method for the Steady-State Analysis of Almost-Periodic Nonlinear Circuits |
| 1356 | -- | 1365 | Qiang Ma 0002, Martin D. F. Wong. NP-Completeness and an Approximation Algorithm for Rectangle Escape Problem With Application to PCB Routing |
| 1366 | -- | 1378 | Meng-Kai Hsu, Yao-Wen Chang. Unified Analytical Global Placement for Large-Scale Mixed-Size Circuit Designs |
| 1379 | -- | 1392 | Rani S. Ghaida, Puneet Gupta. DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies |
| 1393 | -- | 1404 | Xin-Wei Shih, Yao-Wen Chang. Fast Timing-Model Independent Buffered Clock-Tree Synthesis |
| 1405 | -- | 1416 | Xiaochun Yu, R. D. (Shawn) Blanton. Diagnosis-Assisted Adaptive Test |
| 1417 | -- | 1427 | Joon-Sung Yang, Nur A. Touba. X-Canceling MISR Architectures for Output Response Compaction With Unknown Values |
| 1428 | -- | 1438 | Irith Pomeranz. Multicycle Tests With Constant Primary Input Vectors for Increased Fault Coverage |
| 1439 | -- | 1451 | Ansuman Banerjee. Verifying Coalitions in 3-Party Systems |
| 1452 | -- | 1456 | Jyotirmoy Ghosh, Siddhartha Mukhopadhyay, Amit Patra, Barry Culpepper, Tawen Mei. Estimation of dc Performance of a Lateral Power MOSFET Using Distributed Cell Model |
| 1457 | -- | 1461 | Hubert Filiol, Ian O'Connor, Dominique Morche. Analog IC Variability Bound Estimation Using the Cornish-Fisher Expansion |