Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

Volume 31, Issue 7

981 -- 993Bo Liu, Noël Deferm, Dixian Zhao, Patrick Reynaert, Georges G. E. Gielen. An Efficient High-Frequency Linear RF Amplifier Synthesis Method Based on Evolutionary Computation and Machine Learning Techniques
994 -- 1007Xiangyu Dong, Cong Xu, Yuan Xie, Norman P. Jouppi. NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
1008 -- 1018Lin Xie, Azadeh Davoodi. Post-Silicon Failing-Path Isolation Incorporating the Effects of Process Variations
1019 -- 1030Seungwhun Paik, Inhak Han, Sangmin Kim, Youngsoo Shin. Clock Gating Synthesis of Pulsed-Latch Circuits
1031 -- 1040Quan Chen, Shih-Hung Weng, Chung-Kuan Cheng. A Practical Regularization Technique for Modified Nodal Analysis in Large-Scale Time-Domain Circuit Simulation
1041 -- 1049Ming-Chao Lee, Yiyu Shi, Shih-Chieh Chang. Efficient Wakeup Scheduling Considering Both Resource Usage and Timing Budget for Power Gating Designs
1050 -- 1060Chih-Hung Liu, Sy-Yen Kuo, D. T. Lee, Chun-Syun Lin, Jung-Hung Weng, Shih-Yi Yuan. Obstacle-Avoiding Rectilinear Steiner Tree Construction: A Steiner-Point-Based Algorithm
1061 -- 1073Turbo Majumder, Michael Edward Borgens, Partha Pratim Pande, Ananth Kalyanaraman. On-Chip Network-Enabled Multicore Platforms Targeting Maximum Likelihood Phylogeny Reconstruction
1074 -- 1087Hao Shen, Mian Muhammad Hamayun, Frédéric Pétrot. Native Simulation of MPSoC Using Hardware-Assisted Virtualization
1088 -- 1101Vishwanath Natarajan, Hyun Woo Choi, Aritra Banerjee, Shreyas Sen, Abhijit Chatterjee, Ganesh Srinivasan, Friedrich Taenzler, Soumendu Bhattacharya. Low Cost EVM Testing of Wireless RF SoC Front-Ends Using Multitones
1102 -- 1115Mingjing Chen, Alex Orailoglu. On Diagnosis of Timing Failures in Scan Architecture
1116 -- 1128Haralampos-G. D. Stratigopoulos. Test Metrics Model for Analog Test Development
1129 -- 1134Jussi H. Poikonen, Eero Lehtonen, Mika Laiho. On Synthesis of Boolean Expressions for Memristive Devices Using Sequential Implication Logic
1134 -- 1139Yu-Yi Liang, Tien-Yu Kuo, Shao-Huan Wang, Wai-Kei Mak. ALMmap: Technology Mapping for FPGAs With Adaptive Logic Modules
1139 -- 1143Tom Smy, Pavan K. Gunupudi. Robust Simulation of Opto-Electronic Systems by Alternating Complex Envelope Representations