Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

Volume 32, Issue 1

1 -- 0Sachin S. Sapatnekar. Editorial
8 -- 23Puneet Gupta, Yuvraj Agarwal, Lara Dolecek, Nikil Dutt, Rajesh K. Gupta, Rakesh Kumar, Subhasish Mitra, Alexandru Nicolau, Tajana Simunic Rosing, Mani B. Srivastava, Steven Swanson, Dennis Sylvester. Underdesigned and Opportunistic Computing in Presence of Hardware Variability
24 -- 33Fang Gong, Sina Basir-Kazeruni, Lei He, Hao Yu. Stochastic Behavioral Modeling and Analysis for Analog/Mixed-Signal Circuits
34 -- 46Junwhan Ahn, Kiyoung Choi. Isomorphism-Aware Identification of Custom Instructions With I/O Serialization
47 -- 58Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha. Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits
59 -- 72Yan Luo, Krishnendu Chakrabarty, Tsung-Yi Ho. Error Recovery in Cyberphysical Digital Microfluidic Biochips
73 -- 86Karthik V. Aadithya, Alper Demir, Sriramkumar Venugopalan, Jaijeet S. Roychowdhury. Accurate Prediction of Random Telegraph Noise Effects in SRAMs and DRAMs
87 -- 99Ing-Chao Lin, Chin-Hung Lin, Kuan-Hui Li. Leakage and Aging Optimization Using Transmission Gate-Based Technique
100 -- 110Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori. Power-Aware Minimum NBTI Vector Selection Using a Linear Programming Approach
111 -- 123Jongyoon Jung, Taewhan Kim. Statistical Viability Analysis for Detecting False Paths Under Delay Variation
124 -- 137Vaibhav Gupta, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy. Low-Power Digital Signal Processing Using Approximate Adders
138 -- 151Tak-Yung Kim, Taewhan Kim. Resource Allocation and Design Techniques of Prebond Testable 3-D Clock Tree
152 -- 164Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty, Yu-Hua Wu. Counter-Based Output Selection for Test Response Compaction
165 -- 169Shyue-Kung Lu, Huan-Hua Huang, Jiun-Lang Huang, Pony Ning. Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs