| 1641 | -- | 1654 | Ricardo Martins, Nuno C. Lourenço, Nuno Horta. LAYGEN II - Automatic Layout Generation of Analog Integrated Circuits |
| 1655 | -- | 1667 | Jia-Wen Chang, Sheng-Han Yeh, Tsung-Wei Huang, Tsung-Yi Ho. An ILP-Based Routing Algorithm for Pin-Constrained EWOD Chips With Obstacle Avoidance |
| 1668 | -- | 1681 | Gayatri Mehta, Krunalkumar Patel, Natalie Parde, Nancy S. Pollard. Data-Driven Mapping Using Local Patterns |
| 1682 | -- | 1693 | Hans Georg Brachtendorf, Kai Bittner. Grid Size Adapted Multistep Methods for High $Q$ Oscillators |
| 1694 | -- | 1707 | Moongon Jung, David Z. Pan, Sung Kyu Lim. Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations |
| 1708 | -- | 1721 | Jordi Cortadella. Area-Optimal Transistor Folding for 1-D Gridded Cell Design |
| 1722 | -- | 1733 | Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang. ECO Optimization Using Metal-Configurable Gate-Array Spare Cells |
| 1734 | -- | 1747 | Sai Manoj Pudukotai Dinakarrao, Hao Yu, Yang Shang, Chuan Seng Tan, Sung Kyu Lim. Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical-Thermal-Mechanical Coupling |
| 1748 | -- | 1761 | Jinho Lee, Moo-Kyoung Chung, Yeon Gon Cho, Soojung Ryu, Jung Ho Ahn, Kiyoung Choi. Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint |
| 1762 | -- | 1775 | Panagiotis Sismanoglou, Dimitris Nikolos. Input Test Data Compression Based on the Reuse of Parts of Dictionary Entries: Static and Dynamic Approaches |
| 1776 | -- | 1786 | Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer. Test Time Reduction in EDT Bandwidth Management for SoC Designs |
| 1787 | -- | 1800 | Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal. Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors |
| 1801 | -- | 1813 | Aritra Hazra, Rajdeep Mukherjee, Pallab Dasgupta, Ajit Pal, Kevin Harer, Ansuman Banerjee, Subhankar Mukherjee. POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent |
| 1814 | -- | 1818 | Libo Huang, Zhiying Wang, Nong Xiao, Yongwen Wang, Qiang Dou. Dynamic Streamization Model Execution for SIMD Engines on Multicore Architectures |
| 1819 | -- | 1823 | Aayush Prakash, Hiren D. Patel. An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture |
| 1824 | -- | 1828 | Subhadip Kundu, Sankhadeep Pal, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur. A Metric for Test Set Characterization and Customization Toward Fault Diagnosis |
| 1829 | -- | 1833 | Predrag Teodorovic, Stanisa Dautovic, Veljko Malbasa. Recursive Boolean Formula Minimization Algorithms for Implication Logic |