Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

Volume 32, Issue 2

173 -- 174Jiang Hu, Cheng-Kok Koh. Guest editorial: Special section on cross-domain physical optimization
175 -- 188Jackey Z. Yan, Chris Chu. SDS: An Optimal Slack-Driven Block Shaping Algorithm for Fixed-Outline Floorplanning
189 -- 201Shao-Yun Fang, Wei-Yu Chen, Yao-Wen Chang. Graph-Based Subfield Scheduling for Electron-Beam Photomask Fabrication
202 -- 215Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta. Layout Decomposition and Legalization for Double-Patterning Technology
216 -- 227Jia-Wen Chang, Sheng-Han Yeh, Tsung-Wei Huang, Tsung-Yi Ho. Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic Biochips
228 -- 241Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan. Structure-Aware Placement Techniques for Designs With Datapaths
242 -- 246Chih-Long Chang, Iris Hui-Ru Jiang. Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock Gating
247 -- 260JungHee Lee, Youngjae Kim, Galen M. Shipman, Sarp Oral, Jongman Kim. Preemptible I/O Scheduling of Garbage Collection for Solid State Drives
261 -- 274Xiaoming Chen, Yu Wang 0002, Huazhong Yang. NICSLU: An Adaptive Sparse Matrix Solver for Parallel Circuit Simulation
275 -- 288Guoyong Shi. Graph-Pair Decision Diagram Construction for Topological Symbolic Circuit Analysis
289 -- 300Ozgur Sinanoglu. Scan to Nonscan Conversion via Test Cube Analysis
301 -- 312Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman. Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents
313 -- 317Fabio L. Traversa, Fabrizio Bonani. Selective Determination of Floquet Quantities for the Efficient Assessment of Limit Cycle Stability and Oscillator Noise
318 -- 322Mengmeng Li, Ru-Shan Chen, HuaXia Wang, Zhenhong Fan, Qian Hu. A Multilevel FFT Method for the 3-D Capacitance Extraction