| 1373 | -- | 1386 | Po-Cheng Pan, Ching-Yu Chin, Hung-Ming Chen, Tung-Chieh Chen, Chin-Chieh Lee, Jou-Chun Lin. A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation |
| 1387 | -- | 1400 | Yun Liang, Tulika Mitra, Lei Ju. Instruction Cache Locking Using Temporal Reuse Profile |
| 1401 | -- | 1414 | Xuan Wang, Jiang Xu, Zhe Wang, Kevin J. Chen, Xiaowen Wu, Zhehui Wang, Peng Yang, Luan H. K. Duong. An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators |
| 1415 | -- | 1428 | Santiago Pagani, Jian-Jia Chen, Jörg Henkel. Energy and Peak Power Efficiency Analysis for the Single Voltage Approximation (SVA) Scheme |
| 1429 | -- | 1440 | Chia-Hung Liu, Ting Wei Chiang, Juinn-Dar Huang. Reactant Minimization in Sample Preparation on Digital Microfluidic Biochips |
| 1441 | -- | 1454 | Zoha Pajouhi, Swagath Venkataramani, Karthik Yogendra, Anand Raghunathan, Kaushik Roy. Exploring Spin-Transfer-Torque Devices for Logic Applications |
| 1455 | -- | 1466 | Jaeil Lim, Hyunyul Lim, Sungho Kang. 3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability |
| 1467 | -- | 1480 | Honghuang Lin, Peng Li. Circuit Performance Classification With Active Learning Guided Sampling for Support Vector Machines |
| 1481 | -- | 1494 | Xiao Li, Fan Yang, DaKe Wu, Zhenya Zhou, Xuan Zeng. MOS Table Models for Fast and Accurate Simulation of Analog and Mixed-Signal Circuits Using Efficient Oscillation-Diminishing Interpolations |
| 1495 | -- | 1508 | Suleyman Tosun, Vahid Babaei Ajabshir, Ozge Mercanoglu, Özcan Özturk. Fault-Tolerant Topology Generation Method for Application-Specific Network-on-Chips |
| 1509 | -- | 1522 | Sandeep Chatterjee, Mohammad Fawaz, Farid N. Najm. Redundancy-Aware Power Grid Electromigration Checking Under Workload Uncertainties |
| 1523 | -- | 1536 | Mukesh Agrawal, Krishnendu Chakrabarty. Test-Cost Modeling and Optimal Test-Flow Selection of 3-D-Stacked ICs |