External Links

    Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

    Volume 34, Issue 9

    1373 -- 1386Po-Cheng Pan, Ching-Yu Chin, Hung-Ming Chen, Tung-Chieh Chen, Chin-Chieh Lee, Jou-Chun Lin. A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation
    1387 -- 1400Yun Liang, Tulika Mitra, Lei Ju. Instruction Cache Locking Using Temporal Reuse Profile
    1401 -- 1414Xuan Wang, Jiang Xu, Zhe Wang, Kevin J. Chen, Xiaowen Wu, Zhehui Wang, Peng Yang, Luan H. K. Duong. An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators
    1415 -- 1428Santiago Pagani, Jian-Jia Chen, Jörg Henkel. Energy and Peak Power Efficiency Analysis for the Single Voltage Approximation (SVA) Scheme
    1429 -- 1440Chia-Hung Liu, Ting Wei Chiang, Juinn-Dar Huang. Reactant Minimization in Sample Preparation on Digital Microfluidic Biochips
    1441 -- 1454Zoha Pajouhi, Swagath Venkataramani, Karthik Yogendra, Anand Raghunathan, Kaushik Roy. Exploring Spin-Transfer-Torque Devices for Logic Applications
    1455 -- 1466Jaeil Lim, Hyunyul Lim, Sungho Kang. 3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability
    1467 -- 1480Honghuang Lin, Peng Li. Circuit Performance Classification With Active Learning Guided Sampling for Support Vector Machines
    1481 -- 1494Xiao Li, Fan Yang, DaKe Wu, Zhenya Zhou, Xuan Zeng. MOS Table Models for Fast and Accurate Simulation of Analog and Mixed-Signal Circuits Using Efficient Oscillation-Diminishing Interpolations
    1495 -- 1508Suleyman Tosun, Vahid Babaei Ajabshir, Ozge Mercanoglu, Özcan Özturk. Fault-Tolerant Topology Generation Method for Application-Specific Network-on-Chips
    1509 -- 1522Sandeep Chatterjee, Mohammad Fawaz, Farid N. Najm. Redundancy-Aware Power Grid Electromigration Checking Under Workload Uncertainties
    1523 -- 1536Mukesh Agrawal, Krishnendu Chakrabarty. Test-Cost Modeling and Optimal Test-Flow Selection of 3-D-Stacked ICs

    Volume 34, Issue 8

    1209 -- 1222Debashis Banerjee, Shyam Kumar Devarakond, Xian Wang, Shreyas Sen, Abhijit Chatterjee. Real-Time Use-Aware Adaptive RF Transceiver Systems for Energy Efficiency Under BER Constraints
    1223 -- 1235Zidong Du, Avinash Lingamneni, Yunji Chen, Krishna V. Palem, Olivier Temam, Chengyong Wu. Leveraging the Error Resilience of Neural Networks for Designing Highly Energy Efficient Accelerators
    1236 -- 1249Pawel Swierczynski, Marc Fyrbiak, Philipp Koppe, Christof Paar. FPGA Trojans Through Detecting and Weakening of Cryptographic Primitives
    1250 -- 1263Yu-Min Lee, Chi-Wen Pan, Pei-Yu Huang, Chi-Ping Yang. LUTSim: A Look-Up Table-Based Thermal Simulator for 3-D ICs
    1264 -- 1277Chen Wu, Chenchen Deng, Leibo Liu, Jie Han, Jiqiang Chen, Shouyi Yin, Shaojun Wei. An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures
    1278 -- 1290Wing Chiu Jason Tam, Ronald Shawn Blanton. LASIC: Layout Analysis for Systematic IC-Defect Identification Using Clustering
    1291 -- 1294Sourabh Khandelwal, Harshit Agarwal, Juan Pablo Duarte, Kaiman Chan, Sagnik Dey, Yogesh Singh Chauhan, Chenming Hu. Modeling STI Edge Parasitic Current for Accurate Circuit Simulations
    1295 -- 1307Georg T. Becker. On the Pitfalls of Using Arbiter-PUFs as Building Blocks
    1308 -- 1319Andreas Gornik, Amir Moradi, Jürgen Oehm, Christof Paar. A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design, Implementation, and Evaluation
    1320 -- 1333Giovanni Agosta, Alessandro Barenghi, Gerardo Pelosi, Michele Scandale. The MEET Approach: Securing Cryptographic Embedded Software Against Side Channel Attacks
    1334 -- 1343Durga Prasad Sahoo, Phuong Ha Nguyen, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty. A Case of Lightweight PUF Constructions: Cryptanalysis and Machine Learning Attacks
    1344 -- 1357Miltos D. Grammatikakis, Kyprianos Papadimitriou, Polydoros Petrakis, Antonis Papagrigoriou, George Kornaros, Ioannis Christoforakis, Othon Tomoutzoglou, George Tsamis, Marcello Coppola. Security in MPSoCs: A NoC Firewall and an Evaluation Framework
    1358 -- 1369Linus Feiten, Matthias Sauer, Tobias Schubert, Victor Tomashevich, Ilia Polian, Bernd Becker. Formal Vulnerability Analysis of Security Components

    Volume 34, Issue 7

    1045 -- 1058Fanshu Jiao, Sergio Montano, Cristian Ferent, Alex Doboli, Simona Doboli. Analog Circuit Design Knowledge Mining: Discovering Topological Similarities and Uncovering Design Reasoning Strategies
    1059 -- 1069Haotian Liu, Luca Daniel, Ngai Wong. Model Reduction and Simulation of Nonlinear Circuits via Tensor Decomposition
    1070 -- 1081Jaeha Kung, Duckhwan Kim, Saibal Mukhopadhyay. On the Impact of Energy-Accuracy Tradeoff in a Digital Cellular Neural Network for Image Processing
    1082 -- 1095Gage Hills, Jie Zhang 0007, Max Marcel Shulaker, Hai Wei, Chi-Shuen Lee, Arjun Balasingam, H.-S. Philip Wong, Subhasish Mitra. Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations
    1096 -- 1109Shupeng Sun, Xin Li, Hongzhou Liu, Kangsheng Luo, Ben Gu. Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space
    1110 -- 1123Woojoo Lee, Yanzhi Wang, Massoud Pedram. Optimizing a Reconfigurable Power Distribution Network in a Multicore Platform
    1124 -- 1132Irith Pomeranz. A Multicycle Test Set Based on a Two-Cycle Test Set With Constant Primary Input Vectors
    1133 -- 1137Mao-Hsu Yen, Hung-Kuan Yen, Chu Yu. Comment on "On Optimal Hyperuniversal and Rearrangeable Switch Box Designs"
    1138 -- 1142Amit Chhabra, Harsh Rawat, Mohit Jain, Pascal Tessier, Daniel Pierredon, Laurent Bergher, Promod Kumar. FALPEM: Framework for Architectural-Level Power Estimation and Optimization for Large Memory Sub-Systems
    1143 -- 1147Yuan Cao, Le Zhang, Chip-Hong Chang, Shoushun Chen. A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Applications
    1148 -- 1161Jie Zhang, Feng Yuan, Lingxiao Wei, Yannan Liu, Qiang Xu. VeriTrust: Verification for Hardware Trust
    1162 -- 1175Mafalda Cortez, Said Hamdioui, Ali Kaichouhi, Vincent van der Leest, Roel Maes, Geert Jan Schrijen. Intelligent Voltage Ramp-Up Time Adaptation for Temperature Noise Reduction on Memory-Based PUF Systems
    1176 -- 1187Le Zhang, Xuanyao Fong, Chip-Hong Chang, Zhi-Hui Kong, Kaushik Roy. Optimizating Emerging Nonvolatile Memories for Dual-Mode Applications: Data Storage and Key Generator
    1188 -- 1200Begül Bilgin, Benedikt Gierlichs, Svetla Nikova, Ventzislav Nikov, Vincent Rijmen. Trade-Offs for Threshold Implementations Illustrated on AES
    1201 -- 1205Weiwei Shan, Xingyuan Fu, Zhipeng Xu. A Secure Reconfigurable Crypto IC With Countermeasures Against SPA, DPA, and EMA

    Volume 34, Issue 6

    873 -- 874Ramesh Karri, Farinaz Koushanfar, Ozgur Sinanoglu, Yiorgos Makris, Ken Mai, Ahmad-Reza Sadeghi, Swarup Bhunia. Guest Editorial Special Section on Hardware Security and Trust
    875 -- 888Nektarios Georgios Tsoutsos, Michail Maniatakos. The HEROIC Framework: Encrypted Computation Without Shared Keys
    889 -- 902Jeroen Delvaux, Dawu Gu, Dries Schellekens, Ingrid Verbauwhede. Helper Data Algorithms for PUF-Based Key Generation: Overview and Analysis
    903 -- 914Xiaolin Xu, Amir Rahmati, Daniel E. Holcomb, Kevin Fu, Wayne P. Burleson. Reliable Physical Unclonable Functions Using Data Retention Voltage of SRAM Cells
    915 -- 927Suvadeep Hajra, Debdeep Mukhopadhyay. Reaching the Limit of Nonprofiling DPA
    928 -- 936Franck Courbon, Jacques J. A. Fournier, Philippe Loubet-Moundi, Assia Tria. Combining Image Processing and Laser Fault Injections for Characterizing a Hardware AES
    937 -- 946Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich. Fine-Grained Access Management in Reconfigurable Scan Networks
    947 -- 960Ke Huang, Yu Liu, Nenad Korolija, John M. Carulli, Yiorgos Makris. Recycled IC Detection Based on Statistical Methods
    961 -- 971Stephen M. Plaza, Igor L. Markov. Solving the Third-Shift Problem in IC Piracy With Test-Aware Logic Locking
    972 -- 985Chao Chen, José L. Abellán, Ajay Joshi. Managing Laser Power in Silicon-Photonic NoC Through Cache and NoC Reconfiguration
    986 -- 999Xueqian Zhao, Zhonghai Lu. Heuristics-Aided Tightness Evaluation of Analytical Bounds in Networks-on-Chip
    1000 -- 1013Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann. ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing
    1014 -- 1026Fangming Ye, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu. Information-Theoretic Syndrome Evaluation, Statistical Root-Cause Analysis, and Correlation-Based Feature Selection for Guiding Board-Level Fault Diagnosis
    1027 -- 1037Biruk W. Mammo, Valeria Bertacco, Andrew DeOrio, Ilya Wagner. Post-Silicon Validation of Multiprocessor Memory Consistency
    1038 -- 1042Jaeyong Chung, Jibum Kim. Segment Delay Learning From Quantized Path Delay Measurements

    Volume 34, Issue 5

    685 -- 698Jingwei Lu, Hao Zhuang, Pengwen Chen, Hongliang Chang, Chin-Chih Chang, Yiu-Chung Wong, Lu Sha, Dennis J.-H. Huang, Yufeng Luo, Chin-Chi Teng, Chung-Kuan Cheng. ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits
    699 -- 712Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan. Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization
    713 -- 725Hui Geng, Jianming Liu, Pei-Wen Luo, Liang-Chia Cheng, Steven L. Grant, Yiyu Shi. Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach
    726 -- 739Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin, Zhuo Li 0001, Charles J. Alpert, David Z. Pan. Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography
    740 -- 752Sheqin Dong, Jianchang Ao, Fuqi Luo. Delay-Driven and Antenna-Aware Layer Assignment in Global Routing Under Multitier Interconnect Structure
    753 -- 765Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Fumiharu Nakajima, Shigeki Nojima, Toshiya Kotani, Takeshi Ihara, Atsushi Takahashi 0001. Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods
    766 -- 777Jai-Ming Lin, Che-Chun Lin. Placement Density Aware Power Switch Planning Methodology for Power Gating Designs
    778 -- 793Hsi-An Chien, Ye Hong Chen, Szu-Yuan Han, Hsiu-Yu Lai, Ting-Chi Wang. On Refining Row-Based Detailed Placement for Triple Patterning Lithography
    794 -- 807A. Gokcen Mahmutoglu, Alper Demir. Modeling and Simulation of Low-Frequency Noise in Nano Devices: Stochastically Correct and Carefully Crafted Numerical Techniques
    808 -- 821Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, Ramesh Karri. Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures
    822 -- 834Sachhidh Kannan, Naghmeh Karimi, Ramesh Karri, Ozgur Sinanoglu. Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories
    835 -- 848Cristiana Bolchini, Luca Cassano, Paolo Garza, Elisa Quintarelli, Fabio Salice. An Expert CAD Flow for Incremental Functional Diagnosis of Complex Electronic Boards
    849 -- 861Kundan Nepal, Soha Alhelaly, Jennifer Dworak, R. Iris Bahar, Theodore W. Manikas, Ping Guikundan. Repairing a 3-D Die-Stack Using Available Programmable Logic
    862 -- 866Hyunchan Park, Hanchan Jo, Cheol-Ho Hong, Young-Pil Kim, See-hwan Yoo, Chuck Yoo. SSD-Tailor: Automated Customization System for Solid-State Drives
    867 -- 871Ignacio Garcia-Vargas, Raouf Senhadji Navarro. Finite State Machines With Input Multiplexing: A Performance Study

    Volume 34, Issue 4

    501 -- 0Azadeh Davoodi, Jiang Hu, Muhammet Mustafa Ozdal, Cliff C. N. Sze. Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes
    502 -- 514Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang. Region-Based and Panel-Based Algorithms for Unroutable Placement Recognition
    515 -- 528Rickard Ewetz, Cheng-Kok Koh. Cost-Effective Robustness in Clock Networks Using Near-Tree Structures
    529 -- 539Shang-Tsung Yu, Sheng-Han Yeh, Tsung-Yi Ho. Reliability-Driven Chip-Level Design for High-Frequency Digital Microfluidic Biochips
    540 -- 553Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim. Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs
    554 -- 562Caleb Serafy, Ankur Srivastava. TSV Replacement and Shield Insertion for TSV-TSV Coupling Reduction in 3-D Global Placement
    563 -- 576Markus Ahrens, Michael Gester, Niko Klewinghaus, Dirk Müller 0003, Sven Peyer, Christian Schulte 0002, Gustavo E. Téllez. Detailed Routing Algorithms for Advanced Technology Nodes
    577 -- 588Yu-Guang Chen, Wan-yu Wen, Yiyu Shi, Wing-Kai Hon, Shih-Chieh Chang. Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints
    589 -- 602Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan. Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure
    603 -- 614Emad Samuel Malki Ebeid, Franco Fummi, Davide Quaglia. Model-Driven Design of Network Aspects of Distributed Embedded Systems
    615 -- 628Ching-Yi Huang, Zheng-Shan Yu, Yung-Chun Hu, Tung-Chen Tsou, Chun-Yao Wang, Yung-Chih Chen. Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits
    629 -- 641Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho. An Optimal Pin-Count Design With Logic Optimization for Digital Microfluidic Biochips
    642 -- 655Wenxing Zhu, Jianli Chen, Zheng Peng, Genghua Fan. Nonsmooth Optimization Method for VLSI Global Placement
    656 -- 667Mehran Mozaffari Kermani, Niranjan Manoharan, Reza Azarderakhsh. Reliable Radix-4 Complex Division for Fault-Sensitive Applications
    668 -- 681Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji. Time-Division Multiplexing for Testing DVFS-Based SoCs

    Volume 34, Issue 3

    321 -- 331Dani Tannir. Direct Sensitivity Analysis of Nonlinear Distortion in RF Circuits Using Multidimensional Moments
    332 -- 340Reza Azarderakhsh, Mehran Mozaffari Kermani, Kimmo Järvinen. Secure and Efficient Architectures for Single Exponentiations in Finite Fields Suitable for High-Performance Cryptographic Applications
    341 -- 353Sandeep Koranne. Design and Analysis of Silicon Photonics Wave Guides Using Symbolic Methods
    354 -- 366Qing Duan, Jun Zeng, Krishnendu Chakrabarty, Gary Dispoto. Accurate Predictions of Process-Execution Time and Process Status Based on Support-Vector Regression for Enterprise Information Systems
    367 -- 380Fabian Oboril, Rajendra Bishnoi, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori. Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy
    381 -- 394Muhammet Mustafa Ozdal, Aamer Jaleel, Paolo Narváez, Steven M. Burns, Ganapati Srinivasa. Wavelet-Based Trace Alignment Algorithms for Heterogeneous Architectures
    395 -- 408Gabriela Ciuprina, Daniel Ioan, Rick Janssen, Edwin van der Heijden. MEEC Models for RFIC Design Based on Coupled Electric and Magnetic Circuits
    409 -- 421Hengliang Zhu, Yuanzhe Wang, Frank Liu, Xin Li, Xuan Zeng, Peter Feldmann. Efficient Transient Analysis of Power Delivery Network With Clock/Power Gating by Sparse Approximation
    422 -- 432Naval Gupte, Jia Wang. Secure Power Grid Simulation on Cloud
    433 -- 446Bei Yu, Kun Yuan, Duo Ding, David Z. Pan. Layout Decomposition for Triple Patterning Lithography
    447 -- 459Tao Lin, Chris C. N. Chu, Joseph R. Shinnerl, Ismail Bustany, Ivailo Nedelchev. POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints
    460 -- 470Yen-Ting Yu, Geng-He Lin, Iris Hui-Ru Jiang, Charles Chiang. Machine-Learning-Based Hotspot Detection Using Topological Classification and Critical Feature Extraction
    471 -- 482Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang. Stitch-Aware Routing for Multiple E-Beam Lithography
    483 -- 494Emanuele Giaquinta, Anadi Mishra, Laura Pozzi. Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom Instructions
    495 -- 499Ibrahim N. Hajj. On Device Modeling for Circuit Simulation With Application to Carbon-Nanotube and Graphene Nano-Ribbon Field-Effect Transistors

    Volume 34, Issue 2

    161 -- 172Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang, Hui-Fang Tsao. Coupling-Aware Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits
    173 -- 185Lengfei Han, Xueqian Zhao, Zhuo Feng. An Adaptive Graph Sparsification Approach to Scalable Harmonic Balance Analysis of Strongly Nonlinear Post-Layout RF Circuits
    186 -- 198Soumyasanta Laha, Savas Kaya, David W. Matolak, William Rayess, Dominic DiTomaso, Avinash Karanth Kodi. A New Frontier in Ultralow Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects
    199 -- 212Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Ching-feng Yeh, Xin Li, Tsung-Yi Ho. A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise
    213 -- 226Markus Meissner, Lars Hedrich. FEATS: Framework for Explorative Analog Topology Synthesis
    227 -- 237Mengying Zhao, Lei Jiang, Liang Shi, Youtao Zhang, Chun Jason Xue. Wear Relief for High-Density Phase Change Memory Through Cell Morphing Considering Process Variation
    238 -- 251Cláudio Machado Diniz, Muhammad Shafique, Sergio Bampi, Jörg Henkel. A Reconfigurable Hardware Architecture for Fractional Pixel Interpolation in High Efficiency Video Coding
    252 -- 265Donghwa Shin, Massimo Poncino, Enrico Macii, Naehyuck Chang. A Statistical Model-Based Cell-to-Cell Variability Management of Li-ion Battery Pack
    266 -- 279Heechun Park, Taewhan Kim. Synthesis of TSV Fault-Tolerant 3-D Clock Trees
    280 -- 292Mark Po-Hung Lin, Chih-Cheng Hsu, Yu-chuan Chen. Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power Optimization
    293 -- 306Giovanni Mariani, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano. DeSpErate++: An Enhanced Design Space Exploration Framework Using Predictive Simulation Scheduling
    307 -- 320Minghua Tang, Xiaola Lin, Maurizio Palesi. An Offline Method for Designing Adaptive Routing Based on Pressure Model

    Volume 34, Issue 12

    1892 -- 1904Nima Jafarzadeh, Maurizio Palesi, Saeedeh Eskandari, Shaahin Hessabi, Ali Afzali-Kusha. Low Energy yet Reliable Data Communication Scheme for Network-on-Chip
    1905 -- 1917Boxun Li, Peng Gu, Yi Shan, Yu Wang, Yiran Chen, Huazhong Yang. RRAM-Based Analog Approximate Computing
    1918 -- 1927Chia-Hung Liu, Kuo-Cheng Shen, Juinn-Dar Huang. Reactant Minimization for Sample Preparation on Microfluidic Biochips With Various Mixing Models
    1928 -- 1941Yehdhih Ould Mohammed Moctar, Guy G. F. Lemieux, Philip Brisk. Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars
    1942 -- 1953Michael Wainberg, Vaughn Betz. Robust Optimization of Multiple Timing Constraints
    1954 -- 1963Mohsen Riahi Alam, Mostafa Ersali Salehi Nasab, Sied Mehdi Fakhraie. Power Efficient High-Level Synthesis by Centralized and Fine-Grained Clock Gating
    1964 -- 1976Yarui Peng, Dusan Petranovic, Sung Kyu Lim. Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling
    1977 -- 1990Chao Zhang, Wenjian Yu, Qing Wang, Yiyu Shi. Fast Random Walk Based Capacitance Extraction for the 3-D IC Structures With Cylindrical Inter-Tier-Vias
    1991 -- 2003Isuru Nawinne, Haris Javaid, Roshan G. Ragel, Swarnalatha Radhakrishnan, Sri Parameswaran. Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs
    2004 -- 2012Irith Pomeranz. Computation of Seeds for LFSR-Based Diagnostic Test Generation
    2013 -- 2024Vasileios Tenentes, S. Saqib Khursheed, Daniele Rossi, Sheng Yang, Bashir M. Al-Hashimi. DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test
    2025 -- 2038Dominik Erb, Michael A. Kochte, Sven Reimer, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker. Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values
    2039 -- 2048Shi-Yu Huang, Meng-Ting Tsai, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng. Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects
    2049 -- 2053Muhammad Usman Karim Khan, Muhammad Shafique, Lars Bauer, Jörg Henkel. Multicast FullHD H.264 Intra Video Encoder Architecture

    Volume 34, Issue 11

    1701 -- 1703Samarjit Chakraborty, S. Ramesh. Guest Editorial Special Section on Automotive Embedded Systems and Software
    1704 -- 1717Xiaoqing Jin, Alexandre Donzé, Jyotirmoy V. Deshmukh, Sanjit A. Seshia. Mining Requirements From Closed-Loop Control Models
    1718 -- 1729Carles Hernández, Jaume Abella. Timely Error Detection for Effective Recovery in Light-Lockstep Automotive Systems
    1730 -- 1741Chung-Wei Lin, Lei Rao, Paolo Giusto, Joseph D'Ambrosio, Alberto L. Sangiovanni-Vincentelli. Efficient Wire Routing and Wire Sizing for Weight Minimization of Automotive Systems
    1742 -- 1755Chuansheng Dong, Haibo Zeng, Minghua Chen. Online Algorithms for Automotive Idling Reduction With Effective Statistics
    1756 -- 1769Jeyavijayan Rajendran, Aman Ali, Ozgur Sinanoglu, Ramesh Karri. Belling the CAD: Toward Security-Centric Electronic System Design
    1770 -- 1783Armin Alaghi, John P. Hayes. STRAUSS: Spectral Transform Use in Stochastic Circuit Synthesis
    1784 -- 1797Bing Li, Ulf Schlichtmann. Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements
    1798 -- 1807Sandeep Koranne. DÉJÀ VU: An Entropy Reduced Hash Function for VLSI Layout Databases
    1808 -- 1821Johann Knechtel, Evangeline F. Y. Young, Jens Lienig. Planning Massive Interconnects in 3-D Chips
    1822 -- 1835Jyun-Hao Chang, Hsin-I. Wu, Hsien-Lun Pai, Ren-Song Tsay, Wai-Kei Mak. Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations
    1836 -- 1846Shi-Yu Huang, Meng-Ting Tsai, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng. General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects
    1847 -- 1859Amit Kumar 0004, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang. Isometric Test Data Compression
    1860 -- 1872Mottaqiallah Taouil, Mahmoud Masadeh, Said Hamdioui, Erik Jan Marinissen. Post-Bond Interconnect Test and Diagnosis for 3-D Memory Stacked on Logic
    1873 -- 1884Sergej Deutsch, Krishnendu Chakrabarty, Erik Jan Marinissen. Robust Optimization of Test-Access Architectures Under Realistic Scenarios

    Volume 34, Issue 10

    1537 -- 1557Filipp Akopyan, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John V. Arthur, Paul Merolla, Nabil Imam, Yutaka Y. Nakamura, Pallab Datta, Gi-Joon Nam, Brian Taba, Michael Beakes, Bernard Brezzo, Jente B. Kuang, Rajit Manohar, William P. Risk, Bryan L. Jackson, Dharmendra S. Modha. TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
    1558 -- 1568Hassan Eldib, Chao Wang, Mostafa M. I. Taha, Patrick Schaumont. Quantitative Masking Strength: Quantifying the Power Side-Channel Resistance of Software Code
    1569 -- 1576Reza Azarderakhsh, Mehran Mozaffari Kermani. High-Performance Two-Dimensional Finite Field Multiplication and Exponentiation for Cryptographic Applications
    1577 -- 1585Chongxi Bao, Domenic Forte, Ankur Srivastava. Temperature Tracking: Toward Robust Run-Time Detection of Hardware Trojans
    1586 -- 1599Mojtaba Ebrahimi, Adrian Evans, Mehdi Baradaran Tahoori, Enrico Costenaro, Dan Alexandrescu, Vikas Chandra, Razi Seyyedi. Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor
    1600 -- 1612Zhu Wang, Zonghua Gu, Min Yao, Zili Shao. Endurance-Aware Allocation of Data Variables on NVM-Based Scratchpad Memory in Real-Time Embedded Systems
    1613 -- 1626Anatoly Prihozhy, Endri Bezati, Ab Al Hadi Ab Rahman, Marco Mattavelli. Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs
    1627 -- 1638Lorenzo Zuolo, Cristian Zambelli, Rino Micheloni, Marco Indaco, Stefano Di Carlo, Paolo Prinetto, Davide Bertozzi, Piero Olivo. SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives
    1639 -- 1651Xueqian Zhao, Lengfei Han, Zhuo Feng. A Performance-Guided Graph Sparsification Approach to Scalable and Robust SPICE-Accurate Integrated Circuit Simulations
    1652 -- 1663Chris C. N. Chu, Wai-Kei Mak. Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for E-beam Lithography
    1664 -- 1676Guangshuo Liu, Jinpyo Park, Diana Marculescu. 1: Power Constrained Performance Improvement Using Extended Maximize-Then-Swap Algorithm
    1677 -- 1690Yun Liang, Xiaolong Xie, Guangyu Sun, Deming Chen. An Efficient Compiler Framework for Cache Bypassing on GPUs
    1691 -- 1695Carlos Fernando Teodósio Soares, Antonio Petraglia. Automatic Placement to Improve Capacitance Matching Using a Generalized Common-Centroid Layout and Spatial Correlation Optimization
    1696 -- 1699Alexander Korobkov, Amit Agarwal, Subramanian Venkateswaran. Efficient FinFET Device Model Implementation for SPICE Simulation

    Volume 34, Issue 1

    1 -- 0Vijaykrishnan Narayanan, Charles J. Alpert, Sara Dailey. Editorial
    2 -- 15Sachhidh Kannan, Naghmeh Karimi, Ozgur Sinanoglu, Ramesh Karri. Security Vulnerabilities of Emerging Nonvolatile Main Memories and Countermeasures
    16 -- 28Sanghyuk Jung, Yong Ho Song. Garbage Collection for Low Performance Variation in NAND Flash Storage Systems
    29 -- 42Yan Luo, Bhargab B. Bhattacharya, Tsung-Yi Ho, Krishnendu Chakrabarty. Design and Optimization of a Cyberphysical Digital-Microfluidic Biochip for the Polymerase Chain Reaction
    43 -- 51Rene Broich, Hans Grobler. Soft-Core Dataflow Processor Architecture Optimized for Radar Signal Processing
    52 -- 62Roberto Sierra, Carlos Carreras, Gabriel Caffarena, Carlos A. López Bario. A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors
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