| 161 | -- | 172 | Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang, Hui-Fang Tsao. Coupling-Aware Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits |
| 173 | -- | 185 | Lengfei Han, Xueqian Zhao, Zhuo Feng. An Adaptive Graph Sparsification Approach to Scalable Harmonic Balance Analysis of Strongly Nonlinear Post-Layout RF Circuits |
| 186 | -- | 198 | Soumyasanta Laha, Savas Kaya, David W. Matolak, William Rayess, Dominic DiTomaso, Avinash Karanth Kodi. A New Frontier in Ultralow Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects |
| 199 | -- | 212 | Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Ching-feng Yeh, Xin Li, Tsung-Yi Ho. A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise |
| 213 | -- | 226 | Markus Meissner, Lars Hedrich. FEATS: Framework for Explorative Analog Topology Synthesis |
| 227 | -- | 237 | Mengying Zhao, Lei Jiang, Liang Shi, Youtao Zhang, Chun Jason Xue. Wear Relief for High-Density Phase Change Memory Through Cell Morphing Considering Process Variation |
| 238 | -- | 251 | Cláudio Machado Diniz, Muhammad Shafique, Sergio Bampi, Jörg Henkel. A Reconfigurable Hardware Architecture for Fractional Pixel Interpolation in High Efficiency Video Coding |
| 252 | -- | 265 | Donghwa Shin, Massimo Poncino, Enrico Macii, Naehyuck Chang. A Statistical Model-Based Cell-to-Cell Variability Management of Li-ion Battery Pack |
| 266 | -- | 279 | Heechun Park, Taewhan Kim. Synthesis of TSV Fault-Tolerant 3-D Clock Trees |
| 280 | -- | 292 | Mark Po-Hung Lin, Chih-Cheng Hsu, Yu-chuan Chen. Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power Optimization |
| 293 | -- | 306 | Giovanni Mariani, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano. DeSpErate++: An Enhanced Design Space Exploration Framework Using Predictive Simulation Scheduling |
| 307 | -- | 320 | Minghua Tang, Xiaola Lin, Maurizio Palesi. An Offline Method for Designing Adaptive Routing Based on Pressure Model |