External Links

    Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

    Volume 4, Issue 1

    3 -- 11Ting-Hua Chen, Melvin A. Breuer. Automatic Design for Testability Via Testability Measures
    12 -- 22Kazuhiro Ueda, Hitoshi Kitazawa, Ikuo Harada. CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design
    23 -- 30Susanne E. Hambrusch. Channel Routing Algorithms for Overlap Models
    31 -- 41Thomas G. Szymanski. Dogleg Channel Routing is NP-Complete
    41 -- 53A. Poncet. Finite-Element Simulation of Local Oxidation of Silicon
    53 -- 67Jonathan B. Rosenberg. Geographical Data Structures Compared: A Study of Data Structures Supporting Region Queries
    68 -- 76Takao Nishizeki, Nobuji Saito, Kiminobu Suzuki. A Linear-Time Routing Algorithm for Convex Grids
    76 -- 92Andrzej J. Strojwas, Stephen W. Director. A Pattern Recognition Based Method for IC Failure Analysis
    92 -- 98Alfred E. Dunlop, Brian W. Kernighan. A Procedure for Placement of Standard-Cell VLSI Circuits
    99 -- 110G. Bischoff, J. P. Krusius. Technology Independent Device Modeling for Simulation of Integrated Circuits for FET Technologies
    110 -- 117A. M. Mazzone. Three-Dimensional Monte Carlo Simulations--Part II: Recoil Phenomena
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