Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

Volume 4, Issue 4

362 -- 368M. D. Giles, J. F. Gibbons. Calculation of Channeling Effects During Ion Implantation Using the Boltzmann Transport Equation
369 -- 373A. M. Mazzone. Monte Carlo Methods in Defects Migration -- Spontaneous Annealing of Damage Induced by Ion Implantation
374 -- 383J. Albers. Monte Carlo Calculation of One- and Two-Dimensional Particle and Damage Distributions for Ion-Implanted Dopants in Silicon
384 -- 397Peter Pichler, Werner Jüngling, Siegfried Selberherr, Edgar Guerrero, Hans W. Pötzl. Simulation of Critical IC-Fabrication Steps
398 -- 403Thye-Lai Tung, Dimitri A. Antoniadis. A Boundary Integral Equation Approach to Oxidation Modeling
404 -- 407Albert Seidl, Milos Svoboda. Numerical Conformal Mapping for Treatment of Geometry Problems in Process Simulation
408 -- 420Hal R. Yeager, Robert W. Dutton. An Approach to Solving Multiparticle Diffusion Exhibiting Nonlinear Stiff Coupling
421 -- 430Jürgen Lorenz, Joachim Pelka, Heiner Ryssel, Albert Sachs, Albert Seidl, Milos Svoboda. COMPOSITE -- A Complete Modeling Program of Silicon Technology
431 -- 435Craig C. Douglas. A Multilevel Solver for Boundary Value Problems
436 -- 451Randolph E. Bank, William M. Coughran Jr., Wolfgang Fichtner, Eric Grosse, Donald J. Rose, R. Kent Smith. Transient Simulation of Silicon Devices and Circuits
452 -- 461Kiyoyuki Yokoyama, Masaaki Tomizawa, Akira Yoshii, Tsuneta Sudo. Semiconductor Device Simulation at NTT
462 -- 471Conor S. Rafferty, Mark R. Pinto, Robert W. Dutton. Iterative Methods in Semiconductor Device Simulation
472 -- 481Steven E. Laux. Techniques for Small-Signal Analysis of Semiconductor Devices
482 -- 488Toru Toyabe, H. Masuda, Y. Aoki, H. Shukuri, T. Hagiwara. Three-Dimensional Device Simulator CADDETH with Highly Convergent Matrix Solution Algorithms
489 -- 495Joseph W. Jerome. The Role of Semiconductor Device Diameter and Energy-Band Bending in Convergence of Picard Iteration for Gummel s Map
504 -- 512Charles L. Wilson, James L. Blue. Accurate Current Calculation in Two-Dimensional MOSFET Models
513 -- 519H. S. Bennett, D. E. Fuoss. Improved Physics for Simulating Submicron Bipolar Devices
520 -- 526Steven E. Laux, Bertrand M. Grossman. A General Control-Volume Formulation for Modeling Impact Ionization in Semiconductor Transport
527 -- 530A. S. Shieh. On the Solution of Coupled System of PDE by a Multigrid Method
531 -- 535James P. Lavine, Win-Chyi Chang, Constantine N. Anagnostopoulos, Bruce C. Burkey, E. T. Nelson. Monte Carlo Simulation of the Photoelectron Crosstalk in Silicon Imaging Devices
536 -- 540C. Moglestue. A Monte Carlo Particle Study of the Intrinsic Noise Figure in GaAs MESFET s
541 -- 545Umberto Ravaioli, Paolo Lugli, Mohamed A. Osman, David K. Ferry. Advantages of Collocation Methods Over Finite Differences in One-Dimensional Monte Carlo Simulations of Submicron Devices
546 -- 553Jeffrey L. Gray, Mark S. Lundstrom. A Numerical Solution of Poisson s Equation with Application to C-V Analysis of III-V Heterojunction Capacitors
561 -- 574Enrico Sangiorgi, Mark R. Pinto, Stanley E. Swirhun, Robert W. Dutton. Two-Dimensional Numerical Analysis of Latchup in a VLSI CMOS Technology
575 -- 582Bernd Meinerzhagen, Heinz K. Dirks, Walter L. Engl. Quasi-Simultaneous Solution Method: A New Highly Efficient Strategy for Numerical MOST Simulations
609 -- 620Dale E. Hocevar, Ping Yang, Timothy N. Trick, Berton D. Epler. Transient Sensitivity Computation for MOSFET Circuits
621 -- 628S. Inohira, T. Shinmi, M. Nagata, Toru Toyabe, K. Iida. A Statistical Model Including Parameter Matching for Analog Integrated Circuits Simulation
629 -- 635Hong June Park, Choong-Ki Kim. An Empirical Model for the Threshold Voltage of Enhancement NMOSFET s
636 -- 650Chung-Yu Wu, Jen-Sheng Hwang, Chih Chang, Ching-Chu Chang. An Efficient Timing Model for CMOS Combinational Logic Gates
651 -- 661San-Chin Fang, Yannis P. Tsividis, Omar Wing. Time- and Frequency-Domain Analysis of Linear Switched-Capacitor Networks Using State Charge Variables
662 -- 667Makiko Kakizaki, Tsutomu Sugawara. A Modified Newton Method for the Steady-State Analysis
668 -- 684Karem A. Sakallah, Stephen W. Director. SAMSON2: An Event Driven VLSI Circuit Simulator
685 -- 693Eduard Cerny, Jan Gecsei. Simulation of MOS Circuits by Decision Diagrams
694 -- 698P. Conway, Ciaran G. Cahill, W. A. Lane, S. U. Lidholm. Extraction of MOSFET Parameters Using the Simplex Direct Search Optimization Method

Volume 4, Issue 3

166 -- 177Wojciech Maly. Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits
177 -- 189A. F. Franz, G. A. Franz. BAMBI -- A Design Model for Power MOSFET s
189 -- 197Wayne Wei-Ming Dai, Tetsuo Asano, Ernest S. Kuh. Routing Region Definition and Ordering Scheme for Building-Block Layout
198 -- 203Maciej J. Ciesielski. Two-Dimensional Routing for the Silc Silicon Compiler
204 -- 207Hideaki Kobayashi, Charles E. Drozd. Efficient Algorithms for Routing Interchangeable Terminals
208 -- 219James Reed, Alberto L. Sangiovanni-Vincentelli, Mauro Santomauro. A New Symbolic Channel Router: YACR2
220 -- 231Omar Wing, Shuo Huang, Rui Wang. Gate Matrix Layout
232 -- 239Fujio Yamamoto, Sakae Takahashi. Vectorized LU Decomposition Algorithms for Large-Scale Circuit Simulation
239 -- 250William J. Dally, Randal E. Bryant. A Hardware Architecture for Switch-Level Simulation
250 -- 263Tonysheng Lin, Stephen Y. H. Su. The S-Algorithm: A Promising Solution for Systematic Functional Test Generation
264 -- 269Niraj K. Jha, Jacob A. Abraham. Design of Testable CMOS Logic Circuits Under Arbitrary Delays
269 -- 285Giovanni De Micheli, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. Optimal State Assignment for Finite State Machines
285 -- 296Jan M. Rabaey, Stephen P. Pope, Robert W. Brodersen. An Integrated Automated Layout Generation System for DSP Circuits
296 -- 303Edgar Sánchez-Sinencio, Jaime Ramírez-Angulo. AROMA: An Area Optimized CAD Program for Cascade SC Filter Design
303 -- 311Hugo De Man, Ivo Bolsens, E. Vanden Meersch, Johan Van Cleynenbreugel. DIALOG: An Expert Debugging System for MOSVLSI Design
312 -- 321Prithviraj Banerjee, Jacob A. Abraham. A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits
322 -- 328Min-Wen Chiang, J. C. Junior, Chuck Kao. A Simulation Method to Completely Model the Various Transistor I-V Operational Modes of Long Channel Depletion MOSFET s
329 -- 336Masayuki Terai. A Method of Improving the Terminal Assignment in the Channel Routing for Gate Arrays
336 -- 349John K. Ousterhout. A Switch-Level Timing Verifier for Digital MOS VLSI
349 -- 356. A Physical and SPICE-Compatible Model for the MOS Depletion Device

Volume 4, Issue 2

121 -- 126A. M. Patel, N. L. Soong, R. K. Korn. Hierarchical VLSI Routing - An Approximate Routing Procedure
127 -- 134R. F. Vogel. Analytical MOSFET Model with Easily Extracted Parameters
134 -- 142Emil F. Girczyc, Raymond J. A. Buhr, John P. Knight. Applicability of a Subset of Ada as an Algorithmic Hardware Description Language for Graph-Based Hardware Compilation
143 -- 149N. N. Chan, Robert W. Dutton. Lump Partitioning of IC Bipolar Transistor Models for High-Frequency Applications
150 -- 155Martine D. F. Schlag, Ellen J. Yoffa, Peter S. Hauge, Chak-Kuen Wong. A Method for Improving Cascode-Switch Macro Wirability
156 -- 162Wojciech Maly, Zygmunt Pizlo. Tolerance Assignment for IC Selection Tests

Volume 4, Issue 1

3 -- 11Ting-Hua Chen, Melvin A. Breuer. Automatic Design for Testability Via Testability Measures
12 -- 22Kazuhiro Ueda, Hitoshi Kitazawa, Ikuo Harada. CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design
23 -- 30Susanne E. Hambrusch. Channel Routing Algorithms for Overlap Models
31 -- 41Thomas G. Szymanski. Dogleg Channel Routing is NP-Complete
41 -- 53A. Poncet. Finite-Element Simulation of Local Oxidation of Silicon
53 -- 67Jonathan B. Rosenberg. Geographical Data Structures Compared: A Study of Data Structures Supporting Region Queries
68 -- 76Takao Nishizeki, Nobuji Saito, Kiminobu Suzuki. A Linear-Time Routing Algorithm for Convex Grids
76 -- 92Andrzej J. Strojwas, Stephen W. Director. A Pattern Recognition Based Method for IC Failure Analysis
92 -- 98Alfred E. Dunlop, Brian W. Kernighan. A Procedure for Placement of Standard-Cell VLSI Circuits
99 -- 110G. Bischoff, J. P. Krusius. Technology Independent Device Modeling for Simulation of Integrated Circuits for FET Technologies
110 -- 117A. M. Mazzone. Three-Dimensional Monte Carlo Simulations--Part II: Recoil Phenomena