| 166 | -- | 177 | Wojciech Maly. Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits |
| 177 | -- | 189 | A. F. Franz, G. A. Franz. BAMBI -- A Design Model for Power MOSFET s |
| 189 | -- | 197 | Wayne Wei-Ming Dai, Tetsuo Asano, Ernest S. Kuh. Routing Region Definition and Ordering Scheme for Building-Block Layout |
| 198 | -- | 203 | Maciej J. Ciesielski. Two-Dimensional Routing for the Silc Silicon Compiler |
| 204 | -- | 207 | Hideaki Kobayashi, Charles E. Drozd. Efficient Algorithms for Routing Interchangeable Terminals |
| 208 | -- | 219 | James Reed, Alberto L. Sangiovanni-Vincentelli, Mauro Santomauro. A New Symbolic Channel Router: YACR2 |
| 220 | -- | 231 | Omar Wing, Shuo Huang, Rui Wang. Gate Matrix Layout |
| 232 | -- | 239 | Fujio Yamamoto, Sakae Takahashi. Vectorized LU Decomposition Algorithms for Large-Scale Circuit Simulation |
| 239 | -- | 250 | William J. Dally, Randal E. Bryant. A Hardware Architecture for Switch-Level Simulation |
| 250 | -- | 263 | Tonysheng Lin, Stephen Y. H. Su. The S-Algorithm: A Promising Solution for Systematic Functional Test Generation |
| 264 | -- | 269 | Niraj K. Jha, Jacob A. Abraham. Design of Testable CMOS Logic Circuits Under Arbitrary Delays |
| 269 | -- | 285 | Giovanni De Micheli, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. Optimal State Assignment for Finite State Machines |
| 285 | -- | 296 | Jan M. Rabaey, Stephen P. Pope, Robert W. Brodersen. An Integrated Automated Layout Generation System for DSP Circuits |
| 296 | -- | 303 | Edgar Sánchez-Sinencio, Jaime Ramírez-Angulo. AROMA: An Area Optimized CAD Program for Cascade SC Filter Design |
| 303 | -- | 311 | Hugo De Man, Ivo Bolsens, E. Vanden Meersch, Johan Van Cleynenbreugel. DIALOG: An Expert Debugging System for MOSVLSI Design |
| 312 | -- | 321 | Prithviraj Banerjee, Jacob A. Abraham. A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits |
| 322 | -- | 328 | Min-Wen Chiang, J. C. Junior, Chuck Kao. A Simulation Method to Completely Model the Various Transistor I-V Operational Modes of Long Channel Depletion MOSFET s |
| 329 | -- | 336 | Masayuki Terai. A Method of Improving the Terminal Assignment in the Channel Routing for Gate Arrays |
| 336 | -- | 349 | John K. Ousterhout. A Switch-Level Timing Verifier for Digital MOS VLSI |
| 349 | -- | 356 | . A Physical and SPICE-Compatible Model for the MOS Depletion Device |